High-performance computing for static security assessment of large power systems

Abstract

Contingency analysis (CA) is one of the essential tools for the optimal design and security assessment of a reliable power system. However, its computational requirements rise with the growth of distributed generations in the interconnected power system. As CA is a complex and computationally intensive problem, it requires a fast and accurate calculation to ensure the secure operation. Therefore, efficient mathematical modelling and parallel programming are key to efficient static security analysis. This paper proposes a parallel algorithm for static CA that uses both central processing units (CPUs) and graphical processing units (GPUs). To enhance the accuracy, AC load flow is used, and parallel computation of load flow is done simultaneously, with efficient screening and ranking of the critical contingencies. We perform extensive experiments to evaluate the efficacy of the proposed algorithm. As a result, we establish that the proposed parallel algorithm with high-performance computing (HPC) computing is much faster than the traditional algorithms. Furthermore, the HPC experiments were conducted using the national supercomputing facility, which demonstrates the proposed algorithm in the context of N−1 and N−2 static CA with immense power systems, such as the Indian northern regional power grid (NRPG) 246-bus and the polish 2383-bus networks.

Keywords:

• Contingency analysis
• high-performance computing
• large power systems
• N−1 contingency
• N−2 contingency
• security assessment

Acknowledgments

The authors would like to thank IIT (BHU), Varanasi, for providing the PARAM Shivay supercomputing facility to execute the HPC experimentations.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was fully supported by the National Supercomputing Mission (NSM), Department of Science and Technology (DST), Government of India (Reference No.: DST/NSM/R&D_HPC_Applications/2021/03.31).