CAMP: a hierarchical cache architecture for multi-core mixed criticality processors

Abstract

CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems.

GRAPHICAL ABSTRACT

Keywords:

• Mixed-criticality systems
• cache locking
• cache partitioning
• hierarchical cache architecture
• cache coherence protocol
• worst-case execution time (WCET)

Disclosure statement

No potential conflict of interest was reported by the author(s).