SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA

Abstract

This paper proposes an unconventional architecture and algorithm for implementing reservoir computing on FPGA. An architecture-oriented algorithm with improved throughput and architecture designed to reduce memory and hardware resource requirements are presented. The proposed architecture exhibits good performance in terms of benchmarks for reservoir computing. A prediction accelerator for reservoir computing that operates on 55.45 mW at 450 K fps with <3000 LEs is realized by implementing the architecture on FPGA. The proposed approach presents a novel FPGA implementation of reservoir computing focussing on both algorithms and architecture that may serve as a basis for applications of AI at network edge.

GRAPHICAL ABSTRACT

Keywords:

• Reservoir computing
• parallel computing architecture
• FPGA implementation

Acknowledgments

The authors express their sincere gratitude to Tokyo Electron Ltd. for their valuable assistance and cooperation.

Disclosure statement

No potential conflict of interest was reported by the author(s).