An analytical design and analysis of a high gain switched inductor voltage multiplier cell power converter

Abstract

The proposed modified higher gain boost converter employs switched Inductor and multiplier cell-based voltage boosting techniques, as the paper represents. This converter is modelled to enhance the static gain and efficiency. As the designed topology has an incessant source current at its input side, it is ideal for solar PV applications. With a power capacity of 100 W, the proposed topology is designed to work on 24 V source input and 200 V load/output voltage. The load voltage is maintained by a PI controller, which achieves the highest efficiency of 92% under rated load conditions. The converter’s transient performance with the controller is investigated under various situations, including supply voltage variation, reference voltage variation, and load power variation. Finally, the designed converter’s experimental model is created to evaluate the simulated and conceptual results.

KEYWORDS:

• High gain converter
• PI converter
• voltage boosting techniques

1. Introduction

The usage of non-conventional energy sources is growing daily owing to the adverse effects of conventional energy sources. Hence renewable energy is used in the production of electricity. Renewable energy such as solar photovoltaic is used popularly. It can supply in the range of 10 KW, but the issue is that it produces low output voltage. Hence, a boost converter improves the voltage to higher levels. The issue with boost converters is that they have less voltage gain and higher switching stress [1]. Over the years, research has resulted in many circuit designs that can be applied to microgrids that utilize boost converters. As a result, high-gain DC–DC boost converters were required.

Boost converter structures based on impedance networks are developed using one switch with identical capacitors and Inductors [2]. The interleaved converter topologies are employed to reduce the switching stress. The floating interleaved boost converter possesses two modules linked in a cascaded manner at the output and parallel at the source side to produce a less voltage gain with reduced switching loss [3]. The converters presented in Refs [4–6] have a multiplier cell with the boost converter to generate a high static voltage gain. When the multiplier cell is used with a classic step-up converter, the load side voltage is twice that of the classical step-up converter without an increase in the switching voltage. Switch conduction losses are reduced by lowering the drain–source voltage [4]. When the multiplier cell works as a clamping circuit for regeneration, it reduces the problem of EMI generation. When the multiplier cell is combined with the step-up converter, it gives more static gain and less duty cycle [5]. The controlled inverter, which is used instead of a single transistor, reverses the multiplier input current to reduce the power loss by the capacitors. In this circuit, the capacitance of the voltage multiplier cell capacitors is also reduced [6]. Many research have been done to introduce the non-isolated DC–DC power converter topologies. Boosting of input voltage is done by switched Inductor. The concept of capacitor charging in parallel and getting discharged in series is reported in Ref. [7]. This converter has three switches and is operated by two duty ratio. The gain is achieved with a duty ratio of 0.8 to 1; however, getting such a gain is difficult [8].

A capacitor-diode network employed in the non-isolated converters improves the output voltage. The converter has two switches controlled by a single gating signal [9]. For further increase in gain, several boost and quadratic converters are used [10]. Operating the power switch with a duty ratio greater than 0.7 improves the static gain of the converter [11]. A voltage doubler circuit employed in the non-isolated converter topology doubles the output voltage, thereby improving the voltage gain [12]. High-gain extendable power converters structures are presented in Refs [13,14] and use two or more semi-conductor switches to augment the voltage gain. In extended stages, the component count increases, but voltage gain is not changed as much. DC–DC step-up power converters with high voltage gain are employed in real-time situations such as UPS, lamp ballasts, traction and medical applications [15,16]. The significant limitations of isolated DC–DC converters are transformer core saturation and low efficiency [17,18]. The switched capacitor is used with a step-up converter to give more gain in voltage. The continuous input current is obtained without maintaining a high-duty cycle [19]. The converter is designed to supply two different voltage levels, one for low-level loads and the other for high-level loads, which are very suitable for DC micro-grid applications [20].

There is great demand for DC–DC power converters having improved voltage gain with innovative characteristics. This work presents a new lofty step-up DC–DC converter topology that includes a switched inductor, multiplier cell, and only one switch. In addition, the voltage boosting techniques enhanced output voltage with less switching stress, thereby increasing efficiency.

2. Proposed switched inductor–voltage multiplier cell high gain (SI-VMHG) converter topology

The proposed SI-VMHG converter model is designed by integrating the voltage boosting cells such as the switched Inductor and multiplier to augment the voltage gain. The SI-VMHG converter uses a single power switch S, six power diodes D₁ to D₆, high frequency operated inductors L₃, L₂, L₁ and capacitors C₁ to C₅. The resistive load is considered for analysis purposes. The pictorial representation of the SI-VMHG topology is exposed in Figure 1. The SI-VMHG converter is designed by taking into consideration of the subsequent hypothesis. The power switches and power diodes are expected to be ideal; output capacitance has a significant value to get ripple-free output voltage.

Figure 1. Topology of proposed SI-VMHG converter.

3. Operating modes of proposed SI-VMHG converter

Depending on the gating pulse, the proposed model operates in five ways. The switching characteristics of the SI-VMHG model can be found in Figure 2.

Figure 2. Switching waveform of proposed SI-VMHG converter.

Mode 1: For the time range [t₀–t₁], the power semiconductor switch S is turned ON. The D₂, D₃, and D₅ power diodes are biased in the forward direction and D₁, D₄, D₆, D₇, and D₈ diodes are biased in the reverse direction. The L₁ and L₂ inductors are charged with the source voltage V_in. The inductor L₃ and capacitor C₁ get charged due to capacitor voltage C₂. The capacitor C₅ supplies the energy to the load resistor R. The current direction during mode 1 is pictured in Figure 3. The voltage across the L₁, L₂ and L₃ inductors are found using KVL is portrayed in 3 and are expressed in Equations (1)–(4). (1) $\begin{array}{rl}{U}_{\text{L}1}& =U_{\text{in}}\end{array}$(1) (2) $\begin{array}{rl}{U}_{\text{L}2}& =U_{\text{in}}\end{array}$(2) (3) $\begin{array}{rl}{U}_{\text{L3}}& =U_{\text{C}1}-U_{\text{C}2}\end{array}$(3) (4) $\begin{array}{rl}{U}_{\text{C}5}& =U_0\end{array}$(4)

Figure 3. Mode 1 operation.

Mode 2: Power switch S is in ON position during time [t₁–t₂]. The D₂, D₃, and D₈ power diodes are in a conducting state, and D₁, D₄, D₅, D₆, and D₇ diodes are in a non-conducting state. The L₁ and L₂ inductors get charged to the V_in. The capacitors C₃ and C₄ release its energy, whereas the capacitor C₁ gets charged. The capacitor C₅ supplies the power to the load and is displayed in Figure 4. Using Kirchhoff’s Voltage Law, the voltage across the L₁, L₂ and L₃ inductors are found and given in Equations (5)–(7). (5) $\begin{array}{rl}{U}_{\text{L}1}& =U_{\text{in}}\end{array}$(5) (6) $\begin{array}{rl}{U}_{\text{L}2}& =U_{\text{in}}\end{array}$(6) (7) $\begin{array}{rl}{U}_{\text{C}3}-U_{\text{C}5}+U_{\text{C}4}-U_{\text{C}1}+U_{\text{L}3}& =0\end{array}$(7)

Mode 3: The power semiconductor switch S is in the ON position between time interval [t₂–t₃]. The D₂ and D₃ diodes are in conduction mode, and the remaining power diodes are in OFF condition. The L₁ and L₂ inductors continuously store its energy while the capacitor C₅ discharges its charge to the resistor R. The flow of the current path direction is presented in Figure 5. The L₁ and L₂ inductor voltage expressions are specified in Equations (8)–(11) after applying the KVL. (8) $\begin{array}{rl}{U}_{\text{L}1}& =U_{\text{in}}\end{array}$(8) (9) $\begin{array}{rl}{U}_{\text{L}2}& =U_{\text{in}}\end{array}$(9) (10) $\begin{array}{rl}{U}_{\text{L}3}& =0\end{array}$(10) (11) $\begin{array}{rl}{U}_{\text{C}5}& =U_0\end{array}$(11)

Mode 4: During the period [t₃–t₄], the semiconductor switch S is in turned OFF position. The D₁, D₄, D₆, and D₇ power diodes are forward-biased, and D₂, D₃, D₅, and D₈ the diodes are reverse-biased. The capacitor C₂ is charged by discharging the L₁ and L₂ inductors. Similarly, the L₃ inductor, C₂, C₃ and C₄ capacitors are charging due to capacitor C₁. The current flow in the circuit is depicted in Figure 6. The capacitor C₅ discharges its stored energy through R. The voltage across the passive elements is given in Equations (12)–(16). (12) $\begin{array}{rl}& U_{\text{in}}-U_{\text{L}2}-U_{\text{C}2}=U_{\text{L}1}\end{array}$(12) (13) $\begin{array}{rl}& U_{\text{L}2}=U_{\text{in}}-U_{\text{L}2}-U_{\text{L}3}+U_{\text{C1}}-U_{\text{C}4}\end{array}$(13) (14) $\begin{array}{rl}& U_{\text{L3}}=U_{\text{in}}-U_{\text{L}1}-U_{\text{L}2}+U_{\text{C1}}-U_{\text{C3}}\end{array}$(14) (15) $\begin{array}{rl}& U_{\text{C3}}=U_{\text{C4}}\end{array}$(15) (16) $\begin{array}{rl}& U_{\text{C5}}=U_0\end{array}$(16)

Mode 5: For the duration of [t₄–t₅], the semiconductor switch S is in turned OFF position. The D₁, D₄, D₆, and D₇ power diodes are forward-biased, and D₂, D₃, D₅, and D₈ the power diodes are reverse-biased. Now, L₁ and L₂ inductors are discharged, and L₃ inductor is discharged in a positive direction. The C₂, C3, and C₄ capacitors start to charge, and C₁ and C₅ capacitors start to discharge. The direction of the current path is displayed in Figure 7, and the voltage expressions are given in Equations (17)–(20). (17) $\begin{array}{rl}& U_{\text{in}}-U_{\text{L2}}-U_{\text{C2}}=U_{\text{L1}}\end{array}$(17) (18) $\begin{array}{rl}& U_{\text{L2}}=U_{\text{in}}-U_{\text{L2}}-U_{\text{L3}}+U_{\text{C1}}-U_{\text{C4}}\end{array}$(18) (19) $\begin{array}{rl}& U_{\text{C3}}=U_{\text{C4}}\end{array}$(19) (20) $\begin{array}{rl}& U_{\text{C5}}=U_0\end{array}$(20) The static gain expression of the suggested SI-VMHG converter is determined using Equation (21) and stated in Equation (22) using the volt-sec balancing method. (21) $\begin{array}{rl}& {\int }_{t0}^{t1}{U}_{\text{L1}}\text{d}{t}^{\text{I}}+{\int }_{t1}^{t2}{U}_{\text{L1}}\text{d}{t}^{\text{II}}+{\int }_{t2}^{t3}{U}_{\text{L1}}\text{d}{t}^{\text{III}}\\ & +{\int }_{t3}^{t4}{U}_{\text{L1}}\text{d}{t}^{\text{IV}}+{\int }_{t4}^{t5}{U}_{\text{L1}}\text{d}{t}^{\text{V}}=0\end{array}$(21) where I, II, III, IV, and V are operating modes (22) $\begin{array}{r}\frac{U_0}{U_{\text{in}}}=\frac{3\left(1+D\right)}{1-D}\end{array}$(22)

4. Designing of inductor and selection of capacitor

4.1. Design of inductor

The inductors L₁ and L₂ ripple current during the turn-on period of the switch is computed as (23) $\begin{array}{r}\Delta i_{\text{L1}}=\Delta i_{\text{L2}}=\frac{U_{\text{in}}}{\text{L}1}d{\text{T}}_s\end{array}$(23) The derived Inductors L₁ and L₂ values are based on source voltage (V_in), duty ratio (d), switching frequency (f_s) and inductor ripple current (ΔI_L), the inductor values are given as per equation given in (23) (24) $\begin{array}{r}{\text{L}}_1={\text{L}}_2=\frac{{\text{V}}_{\text{in}}d}{{\text{f}}_s\mathrm{\Delta }{i}_{\text{L1}}}\end{array}$(24) The average currents through the inductors L₁ and L₂ are expressed as (25) $\begin{array}{r}{\text{I}}_{\text{L1}}={\text{I}}_{\text{L2}}=\frac{2{\text{I}}_0}{\left(1-d\right)}\end{array}$(25) The inductor L₃ value depends on the capacitor voltage and is designed by using Equation (24) (26) $\begin{array}{r}{\text{L}}_3=\left(\frac{U_{\text{C}3}-U_{\text{C1}}}{\text{d}i}\right)\text{d}t\end{array}$(26)

Figure 4. Mode 2 operation.

Figure 5. Mode 3 operation.

Figure 6. Mode 4 operation.

Figure 7. Mode 5 operation.

4.2. Capacitor selection

The energy stored in the input inductors during mode 5 is transferred to the multiplier capacitor C₂ through diode D₄. The current variations in the diode D₄ are reduced linearly because the capacitor C₂ voltage decreases and maintains constant voltage applied to the resonant inductor. The capacitors C₃ and C₄ get charged in mode 5 where the power switch S is in turn-off condition. The energy stored in the capacitors is expressed as (27) $\begin{array}{rl}{\text{Q}}_{\text{C3}}& ={\text{C}}_3\Delta U_{\text{C}3}=\frac{{\text{I}}_{\text{L1}}}{2}d{\text{T}}_s\end{array}$(27) (28) $\begin{array}{rl}{\text{Q}}_{\text{C4}}& ={\text{C}}_{\text{4}}\Delta U_{\text{C4}}=\frac{{\text{I}}_{\text{L1}}}{2}d{\text{T}}_s\end{array}$(28) The final expression for the selection of capacitors is based on switching frequency (f_s), duty ratio (d), source voltage (U_in), output voltage (U₀) and ripple voltage (ΔU_c). The capacitor C₁–C₅ values are selected based on Equations (29)–(32). (29) $\begin{array}{rl}{\text{C}}_1& ={\text{C}}_2=\frac{{\text{V}}_0\left(1-d\right)}{\text{R}{\text{f}}_s\Delta U_{\text{C1}}}\end{array}$(29) (30) $\begin{array}{rl}{\text{C}}_3& =\frac{d{\text{V}}_0}{\left(1-d\right)\text{R}{\text{f}}_s\Delta U_{\text{C3}}}\end{array}$(30) (31) $\begin{array}{rl}{\text{C}}_4& =\frac{d{\text{V}}_0}{\left(1-d\right)\text{R}{\text{f}}_s\Delta U_{\text{C4}}}\end{array}$(31) (32) $\begin{array}{rl}{\text{C}}_5& =\frac{{\text{P}}_0}{{\text{f}}_s\Delta U_{\text{C}5}}\end{array}$(32)

5. Power loss analysis

The power loss analysis of any converter topology is considered more important because the internal parasitic parameters are included. The internal parasitic resistance of inductor, capacitor and diode are considered for power calculations. The powers consumed by each of the components are computed as below. Let us consider the value of R_L is 10 mΩ.

Power Loss due to inductor: The power loss of the inductors L₁, L₂ and L₃ is derived and given in (33) (33) $\begin{array}{r}{\text{P}}_{\text{L}}\text{ = }{{\text{I}}_{\text{L1}}}^{\text{2}}{\text{R}}_{\text{L}}\text{ + }{{\text{I}}_{\text{L2}}}^{\text{2}}{\text{R}}_{\text{L}}\text{ + }{{\text{I}}_{\text{L3}}}^{\text{2}}{\text{R}}_{\text{L}}\end{array}$(33) The value of I_L1, I_L2 and I_L3 values are calculated using Equations (25) and the power loss is obtained as 1.65 W.

Power Loss due to Capacitors: The power loss of the capacitors is computed by using Equation (34). The value of R_C is 10 mΩ. (34) $\begin{array}{rl}{\text{P}}_{\text{C}}& ={{\text{I}}_{\text{C1}}}^{\text{2}}{\text{R}}_{\text{C}}\text{ + }{{\text{I}}_{\text{C2}}}^{\text{2}}{\text{R}}_{\text{C}}\text{ + }{{\text{I}}_{\text{C3}}}^{\text{2}}{\text{R}}_{\text{C}}\\ & +{{\text{I}}_{\text{C4}}}^{\text{2}}{\text{R}}_{\text{C}}+{{\text{I}}_{\text{C5}}}^{\text{2}}{\text{R}}_{\text{C}}\end{array}$(34) The RMS current values of the capacitors I_C3, I_C4 and I_C5 are calculated using the following equations: (35) $\begin{array}{rl}{\text{I}}_{\text{C3}}& ={\text{I}}_{\text{C4}}=\frac{\sqrt{d}}{1-d}{\text{I}}_0\end{array}$(35) (36) $\begin{array}{rl}{\text{I}}_{\text{C5}}& =\frac{\sqrt{3d^2+d}}{1-d}{\text{I}}_0\end{array}$(36) The computed power loss of the capacitor is 2.18 W.

Power Loss Due to Diode: The power loss associated with the diodes D₁ to D₈ is given in (37). Let, R_D is 17.1 mΩ. (37) $\begin{array}{rl}{\text{P}}_{\text{D\_C}}& ={{\text{I}}_{\text{D1}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D2}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D3}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D4}}}^{\text{2}}{\text{R}}_{\text{D}}\\ & +{{\text{I}}_{\text{D5}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D6}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D7}}}^{\text{2}}{\text{R}}_{\text{D}}\text{ + }{{\text{I}}_{\text{D8}}}^{\text{2}}{\text{R}}_{\text{D}}\end{array}$(37) (38) $\begin{array}{rl}{\text{P}}_{\text{D\_C}}& =\frac{\left(7-d\right){\text{I}}_0^2}{{\left(1-d\right)}^2}\end{array}$(38) Likewise, the forward voltage drop loss of the diode is given in Equation (39). Let, V_f is 0.74 V. (39) $\begin{array}{rl}{\text{P}}_{\text{D\_Vd}}& ={{\text{I}}_{\text{D1\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\text{ + }{{\text{I}}_{\text{D2\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\text{ + }{{\text{I}}_{\text{D3\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\\ & +{\text{I}}_{\text{D4}}\text{\_av}{\text{g}}^{\text{2}}{\text{V}}_{\text{F}}\text{ + }{{\text{I}}_{\text{D5\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\text{ + }{{\text{I}}_{\text{D6\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\\ & +{{\text{I}}_{\text{D7\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\text{ + }{{\text{I}}_{\text{D8\_avg}}}^{\text{2}}{\text{V}}_{\text{F}}\end{array}$(39) (40) $\begin{array}{rl}{\text{P}}_{\text{D\_Vd}}& =\frac{\left(5-d\right){\text{I}}_0}{\left(1-d\right)}\end{array}$(40) where I_{D1_avg}= 2I₀; I_{D2_avg}= I_{D3_avg}= 2dI₀/(1 − d); I_{D4_avg =}I_{D5_avg}= dI₀/(1 − d); I_{D6_avg}= I_{D7_avg}=  I_{D8_avg}= I₀.

The computed power loss of the diode is found to be 3.69 W.

Power Loss Due to Switch: The power loss of the switch is due to switching loss and conduction loss. The power loss associated with the on-state resistance of the switch is given in (41). Let, R_s is 27 mΩ. (41) $\begin{array}{r}{\text{P}}_{\text{S\_C}}={{\text{I}}_{\text{S\_RMS}}}^2{\text{R}}_s\end{array}$(41) The switching loss associated with the switch is given in (42). Let, t_on+ t_off is 74.9 ns. (42) $\begin{array}{r}{\text{P}}_{\text{S\_Sw}}=\frac{1}{2}{\text{V}}_s{\text{I}}_s{\text{f}}_s\left(t_{\text{on}}+t_{\text{off}}\right)\end{array}$(42) where I_{S_RMS}= 16dI₀²/(1 − d)².

The computed power loss of the switch is 2.35 W.

Thus, the total power loss of the proposed high gain converter is calculated by using the following equation: (43) $\begin{array}{r}{\text{P}}_{\text{L\_T}}\text{ = }{\text{P}}_{\text{L}}\text{ + }{\text{P}}_{\text{C}}\text{ + }{\text{P}}_{\text{D}}\text{ + }{\text{P}}_{\text{S}}\text{ = 9}\text{.87 W}\end{array}$(43) The efficiency of the proposed converter is expressed as (44) $\begin{array}{r}\text{Efficiency}=\frac{{\text{P}}_{\text{0}}}{{\text{P}}_{\text{in}}}=91.02\mathrm{\%}\end{array}$(44)

6. Investigation of the proposed SI-VMHG converter with previously designed converter topologies

The static voltage gain, component count, stress in the semiconductor devices, and efficiency of the SI-VMHG converter parameters are compared with various existing converters are tabulated in Table 1. In comparison with the step-up converter, the SI-VMHG topology achieves a 77% increase in voltage gain. The static gain of the converters against the duty ratio is drawn and is shown in Figure 8. The diode switching stress of the SI-VMHG converter with the converter presented in Ref. [2] is equal, but it is 24% less when compared with the converter in Ref. [1]. The amount of switching components in the SI-VMHG converter is 50% lesser than the converter in Ref. [12]. The reduction of component counts leads to a reduction in the power density of the circuit. The simulated efficiency of the proposed SI-VMHG model under rated load conditions is 92%.

Figure 8. Voltage gain against duty ratio.

Table 1. Analysis of the SI-VMHG converter topology with previously designed converters.

Parameter	Boost	[1]	[2]	[12]	Proposed SI-VMHG converter
Static gain	$\frac{1}{1-d}$	$\frac{1+d}{1-d}$	$\frac{2\left(1+d\right)}{1-d}$	$\frac{1+3d}{1-d}$	$\frac{3\left(1+d\right)}{1-d}$
Switch count	1	2	1	2	1
Diode count	1	2	6	2	8
Capacitors count	1	4	3	3	5
Inductors count	1	6	2	3	3
Switching stress	${\text{V}}_0$	$\frac{{\text{V}}_0}{1+d}$	$\frac{{\text{V}}_0}{2}$	$\frac{\text{M}}{1+3d}$	$\frac{{\text{V}}_0}{2}$
Diode stress	${\text{V}}_0$	$\frac{{\text{V}}_0}{1+d}$	$\frac{{\text{V}}_0}{2}$	$\frac{\text{2M}}{1+3d}$	$\frac{{\text{V}}_0}{2}$
Efficiency	80%	89%	83%	89%	92%

7. Results and discussions of simulation

The proposed converter topology is created in MATLAB using the Matlab Simulink tool. It is designed to operate with a 24 V source voltage, a 200 V load voltage, and a 100 W load power. Based on Equations (23)–(28), the values of the power circuit components such as inductors and capacitors are calculated and displayed in Table 2. The voltage at the converter’s output varies for duty ratio, but the converter should maintain the same voltage of 200 V at the output side. The constant load voltage is achieved by using the PI controller. The controller parameters are regulated in such a way as to maintain the voltage at the output constant. The Z-N tuning methodology is adopted to obtain the proportional gain k_P and integral gain k_i values. The block diagram representation of PWM generation using the PI controller is shown in Figure 9. The closed-loop MATLAB simulation of the SI-VMHG converter is pictured in Figure 10. The simulated input and load voltage, current, and power graphical waveforms are shown in Figure 11. The controller maintains a steady voltage of 200 V in the load side of SI-VMHG converter for a voltage of 24 V. The simulated graphical representation of inductors and diodes voltage and current are pictured in Figures 12 and 13.

Figure 9. Generation of PWM signal using PI controller.

Figure 10. Closed-loop simulation diagram of proposed SI-VMHG converter.

Figure 11. Closed-loop simulated waveforms of proposed SI-VMHG converter topology.

Figure 12. Closed-loop simulated current and voltage waveforms of inductors in proposed SI-VMHG converter.

Figure 13. Closed-loop simulated waveforms of inductor current and capacitor voltage of proposed converter.

Table 2. Simulated parameters of proposed SI-VMHG converter.

Parameters	Values
Source voltage	24–48 V
Output/load voltage	200 V
Output/load power	100 W
Switching frequency	20 kHz
Inductor	L1 = L2 = 330 µH, L3 = 1 µH
Capacitor	C1 = C2 = 100 µF, C3 = C4 = 10 µF, C5 = 100 µF

The performance of SI-VMHG converter is analyzed under different conditions, including voltage at the input, setpoint/reference voltage, and output/load power variations.

To investigate the controller’s performance with the SI-VMHG converter topology, different voltage inputs are varied over a wide range of time intervals from 24 to 48 V. The input voltage of 24 V is initially considered at time t = 0 s. The output/load voltage and the load power are regulated to 200 V and 100 W, respectively. A voltage variation of 24–34 V occurred at t = 0.4 s. The change in input voltage tends to enhance the output voltage and load power. The error signal is generated and fed into the controller unit for generating the gating signal to maintain the output voltage and load power. Similarly, the source voltage varies from 34 to 48 V at t = 0.7s; the controller senses the change in output voltage and generates the gating signal for maintaining the voltage at an output of 200 V. The pictorial representation of the input voltage at different time durations is displayed in Figure 14, and the values are tabulated in Table 3.

Figure 14. Performance analysis of proposed SI-VMHG converter under input voltage variation.

Table 3. Source voltage variations.

Voltage on source side (V)	Current on source side (A)	Power on source end (W)	voltage on load side (V)	Current on load side (A)	Power on load end (W)	Efficiency (%)
24	4.58	110	200	0.5	100	90
34	3.207	109	200	0.495	100	91.74
48	2.275	109.2	200	0.5	100	91.57

The controllability of the controller can be studied by altering the setpoint/ reference voltage. On the source side of the converter, the voltage of 24 V is maintained. During time t = 0 s, the setpoint/reference voltage is made at 200 V, and the output voltage and load power are maintained at 200 V and 100 W, respectively. At time t = 0.4 s, the setpoint value is increased from 200 to 220 V; the controller senses the change in voltage and generates the required gating signal to maintain the reference voltage. Likewise, during time t = 0.7 s, the reference voltage decreases from 220 to 180 V. At that time, the controller generates the PWM signal to maintain the reference voltage. The controller took less than 0.02s to maintain the reference value, the load/output power and is presented in Figure 15. The changes in voltage, current, and power values related to the setpoint/reference values variations are tabulated in Table 4.

Figure 15. Performance analysis of proposed SI-VMHG converter under setpoint/reference voltage variation.

Table 4. Reference voltage variations.

Voltage on source side (V)	Current on source side (A)	Power on source end (W)	Reference voltage (V)	voltage on load side (V)	Current on load side (A)	Power on load end (W)	Efficiency (%)
24	5.5	132	220	220	0.55	121	91.66
	4.58	110	200	200	0.5	100	90
	3.644	87.46	180	180	0.446	79.55	90.95
	5.5	132	220	220	0.55	121	91.66

The proposed converter is again tested under different load powers at different durations to assess its working with the controller. During t = 0 s, the converter is operated at half the rated load power of 50 W. Power and voltage are maintained at the output. The load power is increased from 50 to 100 W during time t = 0.5 s. The controller estimates the change in load power variations, and an appropriate gating signal is applied to the power MOSFET to turn on. The change in load power variations at different time durations is shown in Figure 16, and the corresponding variations in voltage, current and power values at the source side and load end are tabulated in Table 5.

Figure 16. Performance analysis of the proposed converter under load power variations.

Table 5. Load power variation.

Voltage on source side (V)	Current on source side (A)	Power on source end (W)	Current on load side (A)	Voltage on load side (V)	Power on load end (W)	Efficiency (%)
24	4.58	110	0.5	200	100	90
	2.763	66.3	0.252	200	50	76
	3.87	93	0.377	200	75	81.07
	4.58	110	0.5	200	100	90

8. Experimental prototype model

A hardware prototype model of the SI-VMHG topology is developed to check the simulation results. Prototype hardware is designed using a voltageof 20 and 240 V at input and output for power at the load of 100 W. The detailed hardware specification of the SI-VMHG topology is tabulated in Table 6. Figure 17 presents the experimental prototype model of the proposed SI-VMHG topology.

Figure 17. Hardware prototype model.

Table 6. Hardware specifications for proposed SI-VMHG converter.

Parameters	Values
Source voltage (Vin)	20 V
Load voltage (V0)	200 V
Output power (P)	100 W
Switching frequency (fs)	20 kHz
Inductor	L1 = L2 = 330 µH, L3 = 1 µH
Capacitor	C1 = C2 = 100 µF, C3 = C4 = 10 µF, C5 = 100 µF
Diode	MUR3060PT
Switch	IRFP9240

The gating pulse for the converter is obtained using a PIC 18F452 microcontroller. The power circuit and the gate driver circuit are presented in Figure 17. In order to obtain a load voltage of 100 V from a source voltage of 10 V, a duty ratio of 0.5 is needed. The load voltage of 86 V is obtained experimentally and is shown in Figure 18(a). Likewise, for a 200 V load voltage, input voltage of 20 V, the experimental output voltage of 199 V is obtained and pictured in Figure 18(b). The inductors (L₁, L₂ and L₃) current waveforms are obtained experimentally and displayed in Figure 18(c,d) and are validated with the simulated waveforms. The diode voltage and current waveforms are found and are shown in Figure 18(e–k). Similarly, the voltage across the switch and current flows through the switch is pictured in Figure 18(l). In order to validate the controllers’ performance, a step change in source voltage variation and load power variations are depicted in Figure 18(m,n).

Figure 18. (a) Gating pulse and output voltage waveforms for the input voltage of 10 V; (b) output voltage waveforms for the input voltage of 20 V; (c) gating pulse and inductor (L₁ and L₂) current waveforms; (d) gating pulse and inductor (L₃) current waveforms; (e) Diode D1 current and voltage waveforms; (f) Diode (D₂ and D₃) current and voltage waveforms; (g) Diode (D₄) current and voltage waveforms; (h) Diode (D₅) current and voltage waveforms; (i) Diode (D₆) current and voltage waveforms; (j) gating pulse and diode (D₇) voltage waveforms; (k) diode (D₈) current and voltage waveforms; (l) switch current and voltage waveforms; (m) step response for input voltage variation waveforms; and (n) step response for load power variation waveforms.

9. Conclusion

The proposed SI-VMHG converter is based on a boost converter that uses switched inductors and voltage multipliers. The proposed topology maintains a continuous current at the source side, making power devices less susceptible to switching stress. The converter is modelled for the voltage rating of 24 V/200 V and power of 100 W. The operating modes and the converter component design values are designed. The proposed SI-VMHG converter simulation studies are performed using MATLAB Simulink tool. The performance behaviour of the SI-VMHG under open loop and closed loop simulations is also done. The PI controller is used to regulate the load voltage of SI-VMHG converter. In addition to that, analyses of the proposed SI-VMHG converter’s performance under various conditions are also provided. Finally, the hardware prototype is modelled, and the experimental result certifies the simulated and theoretical values. From the analysis, it is inferred that the SI-VMHG converter model is compatible with solar PV applications.

Disclosure statement

No potential conflict of interest was reported by the author(s).