Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

Abstract

In every modern ICs the adders are essential components. Adder’s performance has a substantial impact on the architecture of signal processing, controller, the module of filter, the module of data storage, etc., high-speed and area-efficient circuits are the most substantial parameters in every modern integrated circuit. Carry select adder operates at high speed, but it consumes more power due to the large area. The present approach discloses different VLSI hybrid carry select adder architectures. The hybrid technology-based Carry Select adder (CSELA) consists of two stages, namely the Hancarlson adder stage and Hybrid Stage is proposed. In this technique, all the stages (4 bits in each stage) are performed simultaneously to improve the speed and area further. The propagation delays of the proposed adder are the summation of two full adders, seven Multiplexers (4:1) and BEC(3 bit) for producing Cout. The proposed work indicates that the hybrid carry select adder operates at high a speed with a lesser area than the conventional adder. The proposed design is simulated and synthesized in Xilinx ISE 12.1 using Verilog HDL with a family of Vertex6 FPGA devices (Device No. XC6VLX75T, Package FF484, Speed -3). The synthesized report shows that the speed of the proposed adder is improved by 49.06%, 52.61%, 47.58%, 19.08%, 39.9%, 1.25%, 44.43%,19.08%, 44.07% and 71.59% compared to RCA, CBL-based CSELA, CLA, Weinberger BEC-based CSELA,D latched CSELA, Brent Kung CSELA, Brent Kung RCA-based CSELA, CSA Weinberger, Conventional CSELA and Ling CSELA, respectively.

Keywords:

• Multiplexers
• Carry select adder
• Hybrid adder
• Xilinx ISE 12.1
• Verilog HDL

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

V. Thamizharasan

V Thamizharasan is an assistant professor in the Department of Electronics and Communication Engineering at Erode Sengunthar Engineering College. He received a BE degree in electronics and communication engineering from the Erode Sengunthar Engineering College, Erode (Anna University Chennai), in 2008, and an ME degree in VLSI design from Kongu Engineering College, Erode (Anna University, Chennai), in 2010. He has 10 years of teaching experience. He is a life member of ISTE. He published about 6 papers in reputed journals and national and international conferences. His research interests include low power VLSI, VLSI architecture and VLSI signal processing. Corresponding author. Email: [email protected]

N. Kasthuri

N Kasthuri is a professor in the Department of Electronics and Communication Engineering, Kongu Engineering College, India. She received a BE degree in electronics and communication engineering from A C Tech Karaikudi and an ME degree in applied electronics from the Bharathiyar University, Tamilnadu, India. She obtained her doctoral degree in information and communication engineering from Anna University, Chennai, Tamilnadu, India. She has two decades of teaching experience. She has published about 52 papers in reputed journals and national and international conferences. Her research interests cover signal processing, speech signal processing and embedded systems. She received research grants from various funding agencies. She is a Life Member of ISTE. Email: [email protected]