Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

Abstract

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high I_ON of 1.12 × 10⁻⁴ A/µm and robust I_OFF of 9.7 × 10⁻¹⁷ A/µm at V_gs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (C_gd)) and Gate-Source Capacitance (C_gs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low C_gd of 58fF and high C_gs of 6.6fF at V_ds= 0.3 V have been achieved.

KEYWORDS:

• All-around gate
• Device capacitance
• High-density delta (HDD)
• Hetero gate dielectric (HeG) TFET
• Homo gate (HoG) TFET

Acknowledgements

The authors would like to thank Nanoscale Devices, VLSI Circuit and System Design Research Group, IIT Indore, Indore, and VIT Bhopal University for technical support.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Arya Dutt

Arya Dutt received the BTech degree in electrical and electronics engineering in 2018 from the B K Birla Institute of Engineering and Technology, Pilani. He is currently pursuing an MTech degree in VLSI design from the VIT Bhopal University. He has presented and published research papers in reputed conferences based on circuit analysis and optimization. His current research interest includes modeling and simulation of UDSM devices. Currently, he is working on designing and simulating FET devices using TCAD designing tools. Email: [email protected]

Sanjana Tiwari

Sanjana Tiwari received a BE degree in electronics and communication engineering in 2018 from Acropolis Institute of Technology and Research, Indore. She is presently pursuing her MTech degree in VLSI design from VIT Bhopal University. She has published research papers at conferences focused on analog circuit analysis. Her current research interest includes designing and analysis of semiconductor devices like MOSFET. Currently, she is working on an analysis of MOS devices. Email: [email protected]

Mayuresh Joshi

Mayuresh Joshi is pursuing MTech VLSI design at VIT Bhopal University. He has completed his graduation from RTM Nagpur University in electronics and telecommunication engineering. He has published an IEEE conference paper in the analog and RF circuit domain. His research interests are analog, digital, RF, and low-power VLSI circuits. He is currently working on the comparison with various device parameters of a MOSFET device with TFET at the same technology node for low power. Email: [email protected]

Prakhar Nigam

Prakhar Nigam is currently pursuing an MTech degree in VLSI design from the VIT Bhopal University. He received his BE in electronics & communication from Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal. He has published a conference paper on ASIC design analysis and optimization and analog circuits. Currently, he is working on a novel structure of analysis and the performance of Dual-Gate MOSFET and Gate All Around tunnel FET at 18 nm channel length for low-power application. Email: [email protected]

Ribu Mathew

Ribu Mathew received a doctorate degree in electronics engineering from Vellore Institute of Technology (VIT), Chennai Campus. He is a gold medalist in MTech in VLSI design and BTech in electronics and communication engineering. In his doctoral research work, he has contributed to the field of design, modeling, and fabrication of NEMS technology piezoresistive readout-based nano-cantilever sensors for chemical and biological sensing applications. His publications are in reputed journals, such as Nano-micro letters Springer, Journal of Micromechanics and Microengineering (JMM) IOP, Journal of Physics D: Applied Physics IOP, Measurement Elsevier, etc. His research area includes the design, modeling, and fabrication of MEMS/NEMS technology-based sensor and actuator systems, bio-MEMS, analog/RF IC design, SoC design, and device modeling. Email: [email protected]

Ankur Beohar

Ankur Beohar received the MTech degree in VLSI & embedded design system in 2010 from the Maulana Azad National Institute of Technology, Bhopal, and a doctorate degree from IIT Indore in the nanoscale device and its circuit application. Finally, he pursued post doctorate at the Department of School of Electrical Engineering and Computer Science IISER Bhopal. He is currently working as an assistant professor at VIT Bhopal University. He has published several peer-reviewed research papers in reputed SCI journals and International conferences. His research interest includes modeling and simulation of nanoscale device design. Currently, he is working on novel MOS devices such as tunnel FET and its circuit applications for low-power SoC modules. Corresponding author. Email: [email protected]