TCAD Simulation of Novel Recess Gate Common Drain Dual Channel AlGaN/GaN HEMT for Small Signal Performance

Abstract

In this paper, DC and RF characteristics of Recess Gate Common Drain Dual Channel (CDDC) AlGaN/GaN HEMT have been investigated. The performance of the device in terms of the various figures of merits including gate-source capacitance, drain current, transconductance, and channel conductance has been studied for different recess depths. The threshold voltage is found to decrease by shifting right with increasing recess depth, even though with deeper recess, transconductance increases. It has also been observed that the device operates in enhancement mode with a minimum gate recess depth of 15 nm or more. With increasing recess depth, the drain current starts decreasing due to an increase in channel resistance. Use of recess technology with Al graded barrier layer enhances the performance in terms of gm, ft, and fmax which are 0.003 S, 23, and 46 GHz, respectively, but utilizing gate recess technology alone in CDDC HEMT further enhances device performance and the maximum gm, ft, and fmax are 0.0442 S, 28.43, and 59.21 GHz. The CDDC HEMT retain its advantage for specific applications including PA, LNA, and RF switch with optimized gate recess and graded barrier layer parameters.

KEYWORDS:

• Common Drain Dual Channel (CDDC)
• GaN buffer
• Recess gate
• Step-graded Al composition

ACKNOWLEDGEMENTS

The authors would like to thank the Science and Engineering Research Board, Department of Science and Technology (SERB-DST), Govt. of India for providing the funding to develop the research facility under project SPG/2021/001590. This work has been done at the Modeling and Simulation Research Lab, Shaheed Rajguru College of Applied Sciences for Women, University of Delhi, New Delhi, India.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Correction Statement

This article has been corrected with minor changes. These changes do not impact the academic content of the article.

Additional information

Funding

This work was supported by the Science and Engineering Research Board, Department of Science and Technology (SERB-DST), Govt. of India for providing the funding to develop the research facility under project SPG/2021/001590.

Notes on contributors

P. Pal

Praveen Pal received the PhD degree in electronics from University of Delhi in July 2022. In his thesis, he focused on the modeling and simulation of GaN-HEMT device for biosensing applications. He is currently working as postdoc at Nanolab, Indian Institute of Technology Kanpur, India. His current research focuses on characterization and modeling of GaN HEMTs for RF applications especially for RF switch, power amplifiers, and low noise amplifiers. He has authored/co-authored international and national journal papers and conference proceedings. E-mail: [email protected].

Y. Pratap

Yogesh Pratap received the MSc degree in electronics from Kanpur University, India, in 2008, the MTech degree in VLSI design from G.G.S.I.P. University, New Delhi, India, in 2011, and the PhD degree in electronics from the University of Delhi, New Delhi, in 2016. He is currently working as an assistant professor with the Department of Electronic Science, University of Delhi South Campus, New Delhi. He has authored/co-authored more than 50 papers in reputed journals and conference proceedings. His current research interest includes, semiconductor devices reliability for low power VLSI Design, modeling and simulation of nano-electronic devices for biosensing applications. E-mail: [email protected].

S. Kabra

Sneha Kabra is a distinguished expert in the field of electronics, having secured her academic credentials-a bachelor's, master's, and PhD in electronics from the esteemed University of Delhi in 2001, 2003, and 2008 respectively. Her academic journey commenced as a lecturer in the Electronics Department at Acharya Narendra Dev College, University of Delhi, where she served from August 2005 to October 2007. Dr. Kabra then transitioned to the Department of Instrumentation at Shaheed Rajguru College of Applied Sciences, University of Delhi, where she began as an assistant professor in August 2008 and was promoted to the position of associate professor in May 2018. As a senior member of IEEE and a Fellow of IETE, Dr. Kabra has undertaken pivotal leadership roles, including secretary of the IEEE Electron Device Society, Delhi Chapter (2017–2019), Treasurer of IEEE Delhi Section (2020–2022) and secretary of Women in Engineering Affinity Group, IEEE Delhi Section (2019). She currently holds the positions of joint secretary of IEEE Delhi Section, secretary of IEEE Delhi Section-Women in Engineering Affinity Group and EXECOM member of IEEE EDS Delhi chapter. Furthermore, she currently serves as a member of the IEEE India Council Sustainable Development Activities Committee for 2024. Dr. Kabra's research is centered on the modelling, simulation and characterization of advanced deep submicron semiconductor devices applicable to bio-sensing, gas sensing, RF, and digital circuitry. She has an extensive portfolio with over 91 technical publications in esteemed international journals, conferences, and book chapters. Her research acumen is further underscored by the successful completion of three projects one of which was funded by SERB under Ministry of Science & Technology. She is currently overseeing a major research project awarded to her in December 2021. With a keen focus on academic mentorship, Dr. Kabra is presently guiding 2 research scholars and has successfully supervised completion of 3 PhD thesis and 2 MTech dissertations, highlighting her dedication to nurturing emerging talent. In acknowledgment of her excellence in teaching and dedication to education, she was bestowed the Meritorious Teacher Award by the Government of NCT of Delhi in March 2022 under the “Award for College Lecturers” initiative. Corresponding author. E-mail: [email protected].