Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

Abstract

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

Keywords:

• Clock overloading
• CMOS
• D-flip-flop
• low power
• Monte Carlo simulations
• switching activity

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

G. Rajesh Krishna

G Rajesh Krishna received the Btech degree in electronics and communication engineering from Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India, in 2009, and the Mtech degree in digital systems and computer electronics from Rajeev Gandhi Memorial College of Engineering and Technology from Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India, in 2011. He is currently pursuing a PhD degree with the School of Electronics Engineering, VIT-AP University, Amaravati, Andhra Pradesh. From 2011 to 2021, he was an assistant professor in various colleges at Hyderabad. His research interests include the low-power VLSI design and CMOS VLSI design. Mr Rajesh Krishna was a Life Member of The Institution of Electronics and Telecommunication Engineers (IETE). Email: [email protected]

Rohit Lorenzo

Rohit Lorenzo (Senior Member, IEEE) received a PhD degree from NIT Silchar, in 2017. He was a postdoctoral fellow with IIT Guwahati, from 2018 to 2019. He was an assistant professor with NIT Kurukshetra, in 2011, and NIT Delhi, from 2017 to 2018. He is currently an associate professor with the School of Electronics Engineering, VIT-AP University, Amaravati, Andhra Pradesh, India. He has authored various papers in reputed journals and national/international conferences. His research interests include low-power VLSI design, CMOS VLSI design, and memory circuits. Dr Lorenzo received the Gowri Memorial Award from the Institution of Electronics and Telecommunication Engineers, New Delhi. He received the Best Paper Award in “Second IEEE International Conference on Emerging Frontiers in Electrical and Electronic Technologies” organized by NIT Patna, in June 2022. Corresponding author. Email: [email protected]