An FPGA-based balancing of capacitor voltage for multi-level inverter

ABSTRACT

This paper introduces a novel cascaded multilevel inverter circuit configuration aimed at generating a five-level load voltage using a single DC source and a capacitor. In this inverter configuration, an additional switch is added to the charging circuit which helps to charge the capacitor from the DC source. Additionally, an inductor is incorporated to mitigate the substantial charging current during capacitor charging operation. A level-shifted pulse width modulation (LS-PWM) technique is implemented to generate gate pulses for both inverter and charging switches. The capacitor gets charged when an extra switch is enabled and discharged when it is connected to a load. Analysis of charging and discharging of capacitor is described thoroughly in this paper. Each operational mode of the inverter is thoroughly analysed. Furthermore, the proposed five-level inverter setup is designed, and its control logic is implemented using FPGA platform. Subsequently, simulation and experimental investigations are conducted under varied loads and different modulation indices to evaluate the efficacy of the proposed inverter configuration and the respective results are presented.

KEYWORDS:

• Multilevel inverter
• sensor-less voltage balancing of the capacitor
• phase-disposition pulse width modulation
• power loss analysis

Disclosure statement

No potential conflict of interest was reported by the author(s).

Authors’ contributions

All authors have contributed to the study, design, implementation, and drafting of the presented work.

Additional information

Funding

No funding was received to assist with the preparation of this manuscript.