Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

References

• A. Beohar, and S. K. Vishvakarma, “Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width,” IET Micro Nano Lett., Vol. 11, no. 8, pp. 443–5, 2016. DOI: 10.1049/mnl.2016.0202.
   Web of Science ®Google Scholar
• Y. R. Jhan, Y. C. Wu, and M. F. Hung, “Performance enhancement of nanowire tunnel field-effect transistor with asymmetry-gate based on different screening length,” IEEE Electron Device Lett., Vol. 34, no. 12, pp. 1482–4, 2013. DOI: 10.1109/LED.2013.2285156.
   Web of Science ®Google Scholar
• S. Tiwari, A. Dutt, M. Joshi, P. Nigam, R. Mathew, and A. Beohar, “An investigation of a suppressed-drain cylindrical gate-all-around retrograde-doped heterospacer steep-density-film tunneling field-effect transistor,” Springer J. Comput. Electron., Springer, Vol. 5, pp. 1702–10, Jul. 2021.
   Google Scholar
• K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, “Vertical tunnel field-effect transistor,” IEEE Trans. Electron Devices, Vol. 51, no. 2, pp. 279–82, Feb. 2004. DOI: 10.1109/TED.2003.821575.
   Web of Science ®Google Scholar
• A. Chattopadhyay, and A. Malik, “Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor,” IEEE Trans. Electron Devices, Vol. 58, no. 3, pp. 677–83, 2011. DOI: 10.1109/TED.2010.2101603.
   Web of Science ®Google Scholar
• H. Mertens, R. Ritzenthaler, A. Hikavyy, et al., “Gate-All-Around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,” 2016 Symposium on VLSI Technology Digest of Technical Papers , PP. 978–979, 2016.
   Google Scholar
• S. Kim, M. Kim, D. Ryu, et al., “Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet Gate-All-Around MOSFETs,” IEEE Trans. Electron Devices, Vol. 67, no. 6, pp. 2648–52, Jun. 2020. DOI: 10.1109/TED.2020.2989416.
   Web of Science ®Google Scholar
• R. S. Saxena, and M. J. Kumar, “Stepped oxide hetero-material gate trench power MOSFET for improved performance,” IEEE Trans. Electron Devices, Vol. 56, no. 6, pp. 1355–9, Jun. 2009. DOI: 10.1109/TED.2009.2019371.
   Web of Science ®Google Scholar
• H. Jaafar, A. Aouaj, A. Bouziane, and B. Iñiguez, “An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET,” Int. J. Electron. Lett., Vol. 7, no. 4, pp. 458–472, Aug. 2018.
   Google Scholar
• J. Wu, J. Min, and Y. Taur, “Short-channel effects in tunnel FETs,” IEEE Trans. Electron Devices, Vol. 62, no. 9, pp. 3019–24, Jul. 2015. DOI: 10.1109/TED.2015.2458977.
   Web of Science ®Google Scholar
• S. H. Kim, S. Aggarwal, Z. A. Jacobson, et al., “Tunnel field effect transistor with raised germanium source,” IEEE Electron Device Lett., Vol. 31, no. 10, pp. 1107–9, Oct. 2010. DOI: 10.1109/LED.2010.2061214.
   Web of Science ®Google Scholar
• C. K. Pandey, D. Dash, and S. Chaudhury, “Improvement in analog/RF performances of SOI TFET using dielectric pocket,” Int. J. Electron., Vol. 107, pp. 1844–1860, Apr. 2020.
   Web of Science ®Google Scholar
• S. Saurabh, and M. J. Kumar, “Novel attributes of a dual material gate nanoscale tunnel field-effect transistor,” IEEE Trans. Electron Devices, Vol. 58, no. 2, pp. 404–10, Feb. 2011. DOI: 10.1109/TED.2010.2093142.
   Web of Science ®Google Scholar
• A. Beohar, N. Yadav, and S. K. Vishvakarma, “Analysis of trap assisted tunneling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability,” IET Micro Nano Lett., Vol. 12, no. 12, pp. 982–6, Dec. 2017. DOI: 10.1049/mnl.2017.0311.
   Web of Science ®Google Scholar
• S. Saurabh, and M. J. Kumar, “Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis,” Jpn. J. Appl. Phys., Vol. 48, paper no. 064503. 064503, Jun. 2009. DOI: 10.1143/JJAP.48.064503.
   Web of Science ®Google Scholar
• A. Narendiran, K. Akhila, and B. Bindu, “A physics-based model of double-gate Tunnel FET for circuit simulation,” IETE. J. Res., Vol. 62, no. 3, pp. 387–393, Sep. 2015.
   Web of Science ®Google Scholar
• W. Y. Choi, and W. Lee, “Hetero-gate-dielectric tunneling field-effect transistors,” IEEE Trans. Electron Devices, Vol. 57, no. 9, pp. 2317–9, Sep. 2010. DOI: 10.1109/TED.2010.2052167.
   Web of Science ®Google Scholar
• P. P. Goswami, and B. Bhowmick, “Optimization of electrical parameters of pocket doped SOI TFET with L shaped gate,” Springer J. Silicon, Vol. 12, pp. 693–700, Apr. 2019.
   Web of Science ®Google Scholar
• P. Saha, S. Sarkhel, and S. K. Sarkar, “3D modelling and performance analysis of dual material tri-gate tunnel field effect transistor,” IETE Tech. Rev., 1–13, Mar. 2018.
   Web of Science ®Google Scholar
• A. Beohar, N. Yadav, A. P. Shah, and S. K. Vishvakarma, “Analog/RF characteristics of a 3D Cyl underlap GAA-TFET based on a Ge-source using fringing field engineering for low power applications,” Springer J. Comput. Electron., Vol. 17, no. 4, pp. 1650–7, Dec. 2018. DOI: 10.1007/s10825-018-1222-9.
   Web of Science ®Google Scholar
• A. Dutt, S. Tiwari, M. Joshi, P. Nigam, R. Mathew, and A. Beohar. “On-chip Analysis of Etched Drain based Cyl. GAA TFET with Elevated Density Strip”, IOP Conference Series: Materials Science and Engineering, 2021.
   Google Scholar
• “Sentaurusdevicemanual2017.1.” Available: https://www.synopsys.com/silicon/tcad/sentausdevice.html.
   Google Scholar
• A. Dutt, S. Tiwari, A. Upadhyay, R. Mathew, and A. Beohar. “Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance,” Accepted, Silicon Springer, Jan. 2022.
   Google Scholar
• K. Jeon, W. Y. Loh, P. Patel, et al., “Si tunnel Transistors with a novel silicided source and 46mV/dec swing,” Symp on VLSI Tech Dig, 121–122, 2010.
   Google Scholar
• J. H. Kim, H. W. Kim, G. Kim, S. Kim, and B.-G. Park, “Demonstration of fin-tunnel field-effect transistor with elevated drain,” Micromachines. (Basel), Vol. 30, pp. 1–10, 2019.
   Google Scholar
• W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., Vol. 28, no. 8, pp. 743–5, Aug. 2007. DOI: 10.1109/LED.2007.901273.
   Web of Science ®Google Scholar