A highly efficient FPGA implementation of AES for high throughput IoT applications

References

• Alnefaie, S. et al. (2021) ‘A survey on access control in IoT: models, architectures and research opportunities’, Int. J. Security and Networks, Vol. 16, No. 1, pp.60–76. doi: 10.1504/IJSN.2021.112837
   Google Scholar
• Dhanda S.S., Singh B., Jindal P. (2020), “Demystifying Elliptic Curve Cryptography: curve selection, implementation and countermeasures to attacks”, Journal of Interdisciplinary Mathematics, 23(2), 463-470, 2020. doi: 10.1080/09720502.2020.1731959
   Web of Science ®Google Scholar
• Sharma, R., Jindal, P., & Singh, B. (2020). Study and analysis of key generation techniques in the internet of things. Journal of Discrete Mathematical Sciences and Cryptography, 23(2), 373-383. doi: 10.1080/09720529.2020.1721868
   Web of Science ®Google Scholar
• Kumar K et. al., (2021) A lightweight AES algorithm implementation for encrypting voice messages using field programmable gate arrays, Journal of K.S. Univ. Comp. and Info. Sc., Vol. 34(6-B), June 2022, Pages 3878-3885.
   Google Scholar
• Kim, H.K., Sunwoo, M.H. (2019) “Low Power AES using 8-bit and 32-bit datapath optimization for small Internet-of-Things (IoT)”. J Sign Process Syst vol. 91, pp.1283–1289 (2019). doi: 10.1007/s11265-019-01471-8
   Web of Science ®Google Scholar
• N. Ahmad, S.M.R. Hasan, “A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator”, Microelectronics Journal 117 (2021) 105255. doi: 10.1016/j.mejo.2021.105255
   Web of Science ®Google Scholar
• K. Shahbazi and S.B. Ko (2021), “Area-Efficient Nano-AES implementation for Internet of Things Devices” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 29, No. 1, Jan. 2021, pp 136-148. doi: 10.1109/TVLSI.2020.3033928
   Web of Science ®Google Scholar
• M. Jahanbani, N. Bagheri, Z. Norozi, (2020) “Lightweight implementation of SILC, CLOC, AES-JAMBU and COLM authenticated ciphers”, Microprocessors and Microsystems 72 102925. doi: 10.1016/j.micpro.2019.102925
   Web of Science ®Google Scholar
• E. Mobilon, D. S. Arantes, (2021) “100 Gbit/s AES-GCM Cryptography Engine for Optical Transport Network Systems: Architecture, Design and 40 nm Silicon Prototyping”, Microelectronics Journal 116 105229. doi: 10.1016/j.mejo.2021.105229
   Web of Science ®Google Scholar
• M. Maazouz et al., (2021) FPGA implementation of a chaos-based image encryption algorithm, https://doi.org/10.1016/j.jksuci.2021.12.022.
   Google Scholar
• A.M. Garipcan, E. Erdem, “Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique”, ISA Transactions (2021) 117 Page 160–171. doi: 10.1016/j.isatra.2021.01.054
   PubMed Web of Science ®Google Scholar
• Y. Sao et. al., “Co-relation scan attack analysis (COSAA) on AES: A comprehensive approach”, Microelectronics Reliability (2021)123 114216. doi: 10.1016/j.microrel.2021.114216
   Web of Science ®Google Scholar
• S. Sheikhpour et al. “A low cost fault-attack resilient AES for IoT applications”, Microelectronics Reliability (2021) Vol. 123 114202. doi: 10.1016/j.microrel.2021.114202
   Web of Science ®Google Scholar
• X. Guo, M. El-Hadedy, S. Mosanu, X. Wei, K. Skadron, M.R. Stan, (2022) “Agile-AES: Implementation of configurable AES primitive with agile design approach”, INTEGRATION, the VLSI Journal 85 87–96. doi: 10.1016/j.vlsi.2022.04.005
   Web of Science ®Google Scholar
• P. Nannipieri et al., “VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, (2022) Vol. 30, No. 2, Feb. Page 177-186. doi: 10.1109/TVLSI.2021.3129107
   Web of Science ®Google Scholar
• Wei Zhao, Yi Wang, Renfa Li, A unified architecture for dparesistant present, in: 2012 International Conference on Innovations in Information Technology (IIT), IEEE, 2012, pp. 244–248.
   Google Scholar
• S. Subramanian et al., “Reliable hardware architectures for cryptographic block ciphers led and hight, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (10) (2017) 1750–1758. doi: 10.1109/TCAD.2017.2661811
   Web of Science ®Google Scholar
• P. Ahir, M.M. Kermani, R. Azarderakhsh, “Lightweight architectures for reliable and fault detection simon and speck cryptographic algorithms on fpga, ACM Trans. Embed. Comput. Syst. 16 (4) (2017) 1–17. doi: 10.1145/3055514
   Web of Science ®Google Scholar
• Kai Tian, Fault-resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems, Thesis, 2014.
   Google Scholar
• Z. Mishra, B. Acharya (2020), “High throughput and low area architectures of secure IoT algorithm for medical image encryption”, JISA, Vol. 53 (2020) 102533.
   Google Scholar