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Research Articles

A 12T low-power full adder cell with a novel dynamic circuit

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Pages 168-177 | Received 10 Oct 2022, Accepted 18 Jul 2023, Published online: 22 Aug 2023

References

  • Akhter, S., Chaturvedi, S., Khan, S., Bhardwaj, A. 2020. An efficient CMOS dynamic logic-based full adder. 2020 6th International Conference on Signal Processing and Communication (ICSC), pp.226–229.
  • Amini-Valashani, M., Ayat, M., & Mirzakuchaki, S. (2018, April). Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. Microelectronics Journal, 74, 49–59. https://doi.org/10.1016/j.mejo.2018.01.018
  • Hasan, M., Hossein, M. J., Hossain, M., Zaman, H. U., & Islam, S. (2020, August). Design of a scalable low-power 1-bit Hybrid full adder for fast computation. IEEE Transactions on Circuits and Systems—II: Express Briefs, 67(8), 1464–1468. https://doi.org/10.1109/TCSII.2019.2940558
  • Kandpal, J., Tomar, A., Agarwal, M., & Sharma, K. K. (2020, JUNE). High-speed Hybrid-logic full adder using high-performance 10-T XOR–XNOR cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(6), 1413–1422. https://doi.org/10.1109/TVLSI.2020.2983850
  • Naseri, H., & Timarchi, S. (2018, August). Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8), 1481–1493. https://doi.org/10.1109/TVLSI.2018.2820999
  • Rafiee, M., Shiri, N., Sadeghi, A., & MAR. (2022). High-performance 1-bit full adder with excellent driving capability for multistage structures. IEEE Embedded System Letters, 14(1), 47–50. https://doi.org/10.1109/LES.2021.3108474
  • Uyemura, J. P. (2001). Introduction to VLSI circuits and systems. John Wiley & Sons Inc.

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