Enhanced performance of the mechanical respiratory system by FPGA-digital based on PID Controller

Abstract

In mechanical ventilators, ensuring reliable performance and rapid response has become one of the most critical considerations when evaluating non-invasive ventilators. The current design, which utilizes a microprocessor in the embedded system, faces challenges such as low speed, accumulated errors, and jitter phenomena. As a solution, we introduce a Field Programmable Gate Array (FPGA)-based approach to significantly enhance respiratory performance. This paper introduces a pulse generator, quadrature decoder, and digital control scheme to be integrated into a compact controller for the inner loop of the system. Upon receiving user commands, the pulse generator produces signals with varying duty cycles to drive the motor. The feedback signal is monitored using a quadrature decoder, ensuring precise motor operation. To validate the practical effectiveness of our approach, we have implemented a real-world testing system to evaluate the controller’s performance. Our approach achieves a cycle time of approximately 20ns, ensuring real-time performance that cannot be attained with an embedded system. Furthermore, the concurrent framework we employ facilitates faster processing while optimizing resource utilization.

Keywords:

• medical application
• Mechanical ventilator
• FPGA
• Motion control
• Mechanical design

1. Introduction

In the field of driving control, many considerable developments for the servo system that are critical for realizing highly accurate motion (Ruderman et al., 2020) have been gained. Typically, motor-based systems include three control schemes, namely, current control loop, velocity control loop, and position control loop, that are responsible for the three control modes, i.e., torque control mode, velocity control mode, and position control mode. The values of current and velocity are computed entirely by the servo loop, whereas those of the position loop are completed by the digital motion controller. However, the torque control mode can be approved for highly considered response control, as it accelerates performance due to a lessened velocity loop.

In recent times, FPGA has emerged as an alternative solution to address the challenges mentioned above (Gulzar et al., 2018; Ponce et al., 2015). The open architecture of FPGAs and their high density provide advantages over general-purpose microprocessors, making them suitable not only for simple investigations of digital logic but also for designing specific architectures to accelerate computational algorithms such as interpolation (Jokić et al., 2015) and pulse width modulation (PWM) (Younes et al., 2018). Hardware implementation using FPGAs has gained popularity among developers for efficiently creating digital signal processing (DSP) with parallel functions. This approach offers solutions that are ten to a hundred times faster than those achieved using personal computers or DSP-based methods.

As a result, a plethora of related subjects have been introduced. These encompass manipulating the current control scheme with a Xilinx FPGA chip to increase the system loop’s bandwidth (Wang et al., 2022), proposing control methodologies for vector and velocity control of Permanent-Magnet AC servo motors via FPGA solutions (Yang et al., 2022), and devising the design and implementation of a multi-axis motion control chip using FPGA-based techniques and applying it to multi-axis systems (Feng et al., 2020). Additionally, several advanced techniques have been developed, including System-on-Chip (SoC) integration with FPGA for image processing applications (Szabo & Gontean, 2020), cost optimization for BLDC motor drives (Mishra et al., 2021), and neural network-based PID controllers realized through FPGA (Wang et al., 2022).

2. Problem statement

Amidst the backdrop of a global epidemic, there arises a necessity to incorporate the FPGA-implemented driving mechanism into assisted respiratory machines. Notably, contemporary advancements have been frequently applied to a Public Access Ventilator (PAV) (Pearce, 2020), a product of various prevalent techniques. The effectiveness of PAV has been demonstrated, revealing its capability for active ventilation control concerning tidal volume, breathing frequency, and inspiratory pressure. Consequently, a requirement has emerged to replace manual artificial breathing units (AMBU) bags with automated blowers to serve as emergency ventilators (Petsiuk et al., 2020).

Another endeavor involves the creation of an affordable ventilator employing an AMBU bag that isn’t reliant on continuous blower utilization (Marzetti et al., 2021). The study utilizing the AMBU setup demonstrated the feasibility of accomplishing all the functions of a traditional ventilator at a superior cost-efficiency. The automatic AMBU-based ventilator successfully regulated both the breath rate and air volume, thus proving its competitiveness with preceding ventilator designs. This system offers two modes: (a) mandatory ventilation and (b) assisted ventilation. Accordingly, medical personnel have the option to employ the onboard triggering mechanism with an enhanced mode, which adjusts the breathing pattern upon detecting variations in air pressure, or to set time intervals for the respiration pattern.

Subsequently, an open-sourced ventilator featuring portable mechanics was explored and prototyped to administer breaths using a conventional bag-valve mask (BVM). This was achieved through a pivoting cam-mechanism finger actuated by an electric motor. This innovative design eliminates the requirement for a nurse to manually operate the BVM, a solution typically considered short-term. The system incorporates adjustable knobs to regulate the tidal volume tailored to the patient (often 6–8 mL/kg of ideal body weight), a flexible BPM range of 5–30, and the optional inhalation-to-exhalation duration ratio such as 1:2, 1:3, and 1:4, while maintaining a minimum breathing rate (Maia Chagas et al., 2020). This platform functions with an available microprocessor (Frazer et al., 2020), and the associated study provides comprehensive insights suitable as a user guide for technicians, developers, and doctors seeking to replicate a similar ventilator. However, it does not encompass the complete documentation, code, and other requisite elements necessary to qualify as a comprehensive public hardware platform.

Our aim is to integrate FPGA technology into the mechanical ventilator to enhance and maintain the system’s high performance. Historically, much of the related research has focused on ventilator-associated medical conditions, such as pneumonia (Zhao et al., 0000) or lung injuries (Gaver et al., 2020). In recent times, mechanical power has garnered significant attention for studying the impacts of ventilator parameters (Giosa et al., 2019; Silva et al., 2019). Within the realm of mechatronic engineering, considerable efforts have been invested in developing robust designs and controls for ventilators (Arcos-Legarda & Tovar, 2021; Martell et al., 2022; Ramos-Paz et al., 2020). While several learning techniques (Behravan et al., 2019; Marzetti et al., 2021) have been explored, there is still a lack of a high-tech solution that encompasses a combination of logic control circuits and hardware programming.

In this paper, we present a novel approach aimed at developing an advanced solution for non-invasive ventilators. Our design focuses on enhancing the overall characteristics, including reliable performance and rapid response, of mechanical ventilators crucial for emergency situations. Given that the combined actions of driving actuators and varying control signals can lead to challenges in ensuring adequate air supply and swift responsiveness, the task of designing both computational mechanics and electronics becomes intricate to achieve stable movement while maintaining accurate tracking. To address these challenges, we propose an FPGA-based approach that yields superior results in achieving precise ventilator control. Employing a finite-state machine (FSM), we integrate digital proportional-integral-derivative (PID) control in a discretized form. Each component of the controller is comprehensively described to compute their respective values. Additionally, we introduce a positioning decoder to translate feedback values from the DC motor to the main module. Brief explanations and implementations of other developments are also provided. The remainder of this work is structured as follows: Section III presents a detailed framework of the proposed design. The design process is systematized through various theoretical computations. In Section IV, we detail the implementation of the PID controller in digital form, covering theory and computation, realization of PID control, exemplification, and UART communication. To demonstrate the effectiveness and feasibility of our design, we conduct practical tests and present experimental results in Section V. Finally, in Section VI, we draw several conclusions that highlight the potential for further development and broader applications of this method.

3. Framework of the proposed design

An overview of the framework design is shown in Figure 1. The key components of this system consist of the controlled object such as DC servo, decoder, PID scheme for computational controller, PWM module, H-bridge circuit to produce the corresponding control signal, UART module with FIFO buffer to communicate with computer. The sensing signals from two channels of encoder in DC servo are transmitted to decoder. This decoding module would estimate and yield two parameters: positioning encoder and velocity. Depending on the target control, one of two signals is elected to transmit to personal computer via UART communication as well as conduct to the computational error in comparison to reference signal. Afterward, these errors are sent to PID controller in order to identify the control signal which is passed to PWM module to generate pulses. Later, the pulse signal is transferred to H-bridge circuit.

Figure 1. Diagram of general framework for the proposed design.

4. Design of the digital PID controller

Deriving from our motivations, PID scheme is digitized via logic resources, concurrent computation and synthesis. The design of this method warrants the advantages of hardware programming as well as the real-time performance of mechanical ventilator.

4.1. Theory and computational method

The PID scheme of the continuous system is given as

(1) $\mathit{u}\left(\mathit{n}\right)=\mathit{MV}\left(\mathit{t}\right)=K_p\mathit{e}\left(\mathit{t}\right)+K_i{\int }_0^t\mathit{e}\left(\mathit{\tau }\right)\mathit{d\tau }+K_d\frac{d}{\mathit{dt}}\mathit{e}\left(\mathit{t}\right),$(1)

To realize this controller logically and reasonably in the digital platform, i.e. FPGA (Field-Programmable Gate Array), Equation (1)(1) $\mathit{u}\left(\mathit{n}\right)=\mathit{MV}\left(\mathit{t}\right)=K_p\mathit{e}\left(\mathit{t}\right)+K_i{\int }_0^t\mathit{e}\left(\mathit{\tau }\right)\mathit{d\tau }+K_d\frac{d}{\mathit{dt}}\mathit{e}\left(\mathit{t}\right),$(1) should be converted to one for the discrete system

(2) $\mathit{u}\left(\mathit{n}\right)=\left(K_p+K_d\right)\mathit{e}\left(\mathit{n}\right)+K_i\sum _0^n\mathit{e}\left(\mathit{j}\right)-K_d\mathit{e}\left(\mathit{n}-1\right),$(2)

In the above equation, each factor must be modelled to compute by the functional block. In Figure 2, it is necessary to implement below functional blocks:

Figure 2. Block diagram of the PID computation.

• Multiplier: to proceed the multiplication in the expression, the multiplier 18 × 18is a set of logic units specialized for multiplying two integers up to 18-bit. This multiplier is configured to work in the mode of 3-stage pipeline, in which the input is fed continuously without having to wait for the output to stabilize. The time duration for this computational process is three pulse clocks. By using the IP core from Xilinx, the resource is saved together with ensuring both the speed and the accuracy.

• Adder: In the same way, the adder is also configured to handle in the mode of 3-stage pipeline. Since the addition is simpler than the multiplication, there is no hardware specialized for this process. It should directly use the LUT and Slices of FPGA platform to complete the addition.

In this case, the FSM (Finite State Machine) method is deployed for computation. Totally, it requires nine states to estimate Equation (2)(2) $\mathit{u}\left(\mathit{n}\right)=\left(K_p+K_d\right)\mathit{e}\left(\mathit{n}\right)+K_i\sum _0^n\mathit{e}\left(\mathit{j}\right)-K_d\mathit{e}\left(\mathit{n}-1\right),$(2) as below:

• One state to update the system parameters $K_p,K_i,K_d$ is temporarily zero

• One state to update the system parameters $K_p+K_d$

• Seven states to compute the components in this equation and sum up

Consequently, the computational results of PID controller are nine clock pulses after updating the values of SP (Set Point) and PV (Process Variable). At that time, the signal o_valid would be pulled up and o_un would carry out the output value.

4.2. Realization of PID control

In Figure 3, the PID controller is generally shown to depict the input components such that:

Figure 3. General inputs/outputs of the PID computation.

The input parameters of this block consist of

• $K_p,K_i,K_d$: the control parameters of PID scheme which are the proportional gain, integral and derivative gain. These gains are input with the type of unsigned 16-bit integer

• $\mathit{PV}$: the measured value to control such position or velocity. It also belongs to unsigned 16-bit integer

• $\mathit{SP}$: the set-point value such position or velocity, unsigned 16-bit integer

• i_clk: the clock pulse signal from digital source

  i_rst: the reset signal

Additionally, the output parameters of this block include

• o_un: the output result after computing from PID scheme, directly connected to PWM module. The value of o_un is an integer, unsigned 32-bit

• overflow: this flag to identify the overflow signal in computing. If it is high level, the overflow in computing occurs

• o_valid: this signal to determine that the output of PID control is stable. If it is high level, the computation of PID scheme is completed

4.3. Exemplification of PID control

To exemplify these computations correctly, it is often simulated to launch the level of set-point and that of error. Simultaneously, the output of this controller is monitored. If the simulated outputs provide the value which exactly matches to those computed by software, it could be concluded that the computational work is correct. The results of computations from software are listed as Table 1.

Table 1. Example of computational result from the PID scheme

Sp	Pv	Kp	Ki	Kd	e(n)	e(n-1)	sigma	Un
450	300	1	10	0	150	0	150	1650
450	330	1	10	0	120	150	270	2820
450	360	1	10	0	90	120	360	3690
450	390	1	10	0	60	90	420	4260
450	420	1	10	0	30	60	450	4530
450	450	1	10	0	0	30	450	4500
450	480	1	10	0	−30	0	420	4170
450	510	1	10	0	−60	−30	360	3540
450	540	1	10	0	−90	−60	270	2610

4.4. UART communication

UART, Universal asynchronous receiver transmitter, is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to the most significant, framed by start and stop bits so that precise timing is handled by the communication channel. The electric signalling levels are handled by a driver circuit external to the UART. Two common signal levels are RS-232, a 12-volt system, and RS-485, a 5-volt system. Early teletypewriters used current loops.

In Figure 4, UART communication is a method of transmitting data synchronously between two interfaces. UART will be using two lines, one inbound (Tx) and the other one (Rx). The output is transmitted sequentially, with a possible length of 7, 8 or 9 bits with 1 bit check. Before exchanging data, UART transmits 1 low bit as a start signal. After the data is finished, the UART transmits the high 1 bit to indicate the end of the data. The frequency of UART is variable, of which a rate of 9600 bps is commonly used.

Figure 4. Data frame of UART communication.

Since UART communication can only access 8 bits of data at a time, if this protocol wants to transfer 32 data bits, it must access four times. However, waiting for the UART signal to transmit data can cause the delay in data transmission and sample collection. Therefore, these works of data transmission and sampling should be done individually. The data to be tracked will be sampled cyclically. That value will be saved to a First In First Out (FIFO) buffer. The output will be written to 32 bits at a time.

FIFO is designed to use 18kb RAM of the FPGA. Due to the nature of the data being 32 bits, it should use RAM at only 36 bits x 512 addresses when dealing with sampled data. Also, when communicating with the UART, the RAM would act as if it is being operated at 8 bits x 2048 addresses. The arrangement for RAM memory in Spartan 3A is given in Figure 5.

Figure 5. Memory arrangement in RAM.

The UART would read a group of 8 bits at a time from the FIFO and transmit it. After transmitting 4 times, the UART would proceed to the next address and repeat the cycle. For the UART communication standard, it does not need to add a clock generator. This clock offset would ensure that the data is properly transmitted between the computer and the FPGA, generate clock pulses to billions of global clocks, subdivide them according to the clock standard.

5. Results of study

From above designs, there is a need to validate the properness and effectiveness in our approach. Several test components are realized as well as the proposed method is verified in the real-world platform. Additionally, total resource of device utilization if using our design is summarized. The competitive performance between the proposed developments and the others is also indicated.

5.1. Realization of the communication protocol

The UART module realized by Verilog programming language is demonstrated as Figure 6. The inputs are explained in detail:

Figure 6. The realization of UART structure in FPGA environment.

• data_in: save the data which is entered. For each sampling cycle, the data is collected. This form would appear on this input, in parallel and would be written to the FIFO

• clk: the clock pulse signal

• i_wr_uart: the writing signal which allows data from pin data_in to write into FIFO buffer, if this signal is pulled to high level

• reset: the reset signal

Similarly, the outputs are

• tx: the transmitting signal of UART, it would be connected to a converter TTL-USB to communicate with serial port of USB

To validate the operation of UART, there are two methods: simulation and real. The simulation method is performed by every sampling cycle, it sends a 32-bit fixed data input. This data would be stored in the FIFO memory. By observing the output string on the TX switch and the data in the FIFO memory, it could check the operation of the UART. It is assumed that there is a need to access the data string as a 32-bit integer with value 246,910, or a bit value of 0000_0000_0000_0011_1100_0100_0111_1110, the simulation result would be obtained as in Figure 7. To access data with 8-bit, data format includes 1 start bit, 1 stop bit, 0 parity bit. UART accesses the LSB first. For the actual check, TTL and USB converter module are required. The predefined starting character would be transmitted and check it out carefully at the same serial port. Data would be transmitted at a rate of 9600bps. A python program would read the serial number, process the data, and display the terminal window.

Figure 7. Result for validation of UART communication.

5.2. Arduino module

The main role of Arduino module is to provide 3,3V power for the positioning sensor to work. The Arduino is powered separately, and the GND pin is shared with the GND of the rest of the circuit. In addition, the Arduino also acts as a voltage translator. Data sent from the Encoder cannot cover the working area of the opto-isolating module due to the 3,3V implementation. Instead of directly sending to the isolator, the encoder would switch to the Arduino module. In this stage, the Arduino would convert this signal to 5V and put it into the isolator. To guarantee the minimum delay, the digitalRead and digitalWrite functions would not be utilized, but instead, we would manipulate directly on each pin.

5.3. PC817

PC817 is an opto-isolator module. The module is connected as the isolation section between the driving motor and the input of the FPGA because this board cannot withstand the EMF surge that the motor generates during operation. The output is sent to the same IN pin to the LED terminal in the module. The output is selected from V1. The port must be configured with V1 as the input port and the concurrency is not high-pass. Although this module provides a class of isolation between the motor and the FPGA, but the limited power is transmitted to the maximum. This efficiency will depend on the response of the LEDs in the module. In this project, PC817 has been fully satisfied when the engine is operating at maximum speed, so we can use it.

5.4. Converter from TTL to USB

To be able to communicate between the UART generated by the FPGA, TTL output, to the computer, a converter is needed to translate from TTL signal to input of USB. The module used in this project is the PL2303 module which supports data transmission in standard format, and is widely used. At the same time, the PL2303 needs to take full advantage of the states of accessing information through the same COM port such large buffer, block communication, automatic traffic to manipulate flow. Since PLC2303 provides large bandwidth, it is suitable for communication demand between FPGA and computer.

5.5. Hardware platform

The open-source design of mechanical single-limb ventilator that includes one hose for the respiratory circuit, exhalation occurs through a single orifice located at the distal end of the circuit, is completely manufactured as Figure 8. It is designed to be highly reproducible, simple in fabrication, easy maintenance and usage for emergency case, pandemics and in developing and under-resourced communities. The design of the device and software was administered by ISO standards. This platform can be invented from voluntarily available components, public microcontroller with open-source electronics and schematic. Non-invasive ventilation, which can be easily controlled by a simple input and user interface, was elected to be the most effective to cure the largest number of patients.

Figure 8. Real platform of non-invasive ventilator.

5.6 Hardware platform

The open-source design of mechanical single-limb ventilator that includes one hose for the respiratory circuit, exhalation occurs through a single orifice located at the distal end of the circuit, is completely manufactured as Figure 8. It is designed to be highly reproducible, simple in fabrication, easy maintenance and usage for emergency case, pandemics and in developing and under-resourced communities. The design of the device and software were administered by ISO standards. This platform can be invented from voluntarily available components, public microcontroller with open-source electronics and schematic. Non-invasive ventilation, which can be easily controlled by a simple input and user interface, was elected to be the most effective to cure the largest number of patients.

The overall scheme of this platform is clearly depicted as Figure 9. In general, there are two loops to handle the operation of ventilator. The first one is outer loop which measures both the air flow and air pressure. This loop is mainly responsible to handle the inclusive operations from user input, computing the error and converting to command signal, pulse-based generation and driving the mechanical architecture to supply the necessary quantity of air. The second loop is inner one which primarily focus on ensuring the motor operation. In such case, FPGA module has been implemented into inner loop and the isolation module is added to guarantee that there are no reverse effects from driving motor to small signal module.

Figure 9. Overall scheme of outer loop and FPGA-based inner loop.

Thanks to hardware programming board, the physical hardware could be reduced and converted into coding. The digital PID controller is embedded as key control scheme to manipulate DC motor. In fact, it includes several units of multiplication and addition which is demonstrated as Figure 10. By using our approach, the cycle time ensures the real-time performance, approximately 20 ns. In this design, the concurrent computation which allows faster processing and economical resources, should be divided into two stages: the first stage and the second stage. Optionally, the first stage must be activated primarily. However, in some computations, it requires to trigger both. The result of control signal from digital PID scheme is illustrated as Figure 11. Totally, it takes seven cycling times for digital computation which comprises two operators such multiplication and addition. In each mathematical operator, two stages are simultaneously computed to produce the values of coefficients. According to previous computation, they are continuously processed in current cycle. In Table 2, a summary of the device utilization characteristics for the logic circuit is given. The proposed method certifies that only a few of logic resources are utilized and the technical specifications of this system are preserved.

Figure 10. Computational stage of multiplication and addition.

Figure 11. Result of PID controller realized by FPGA.

Table 2. Summary of the device utilization characteristics in our approach

List of used resources
Logic utilization	Total	Used
Number of flip-flops	1,703	23%
Number of LUTs	4,190	61%
Logic distribution
Number of occupied slices	2,761	72%

To the best of our knowledge, the competitive performance between the proposed method and the others is depicted as Table 3. In each study, they present the own purpose in respect to specific assumptions and theories. For this work, it is hopefully appreciated that the real-time performance which is very important for respiratory system, could be preserved in the mechanical ventilator.

Table 3. List of comparative performance between our approach and related studies

Author(s)	Tidal volume	Driving mechanism	Motor specification	Control scheme	Achievement(s)
(Ramos-Paz et al., 2020)	AMBU (N/A)	Slider crank	DC motor	Sliding mode control	A robust control scheme guarantees the trajectory tracking control corresponding to the breathing profiles required by the patients
(Arcos-Legarda & Tovar, 2021)	Bag valve (200-600 ml)	Strap-driven	DC gearmotor	Active disturbance rejection control	It delivers oxygen to the patient completely while maintaining a PEEP and the respiratory circuit in respect to both internal and external perturbations
(Marzetti et al., 2021)	Bellow tube (0,2–1,5 L)	Cable wire	3D printer stepper motor	K-means unsupervised learning	Both learning pase and training pase provide the superior ability to detect any failure
Our approach	AMBU (200-800 ml)	Finger-like mechanics	DC gearmotor	FPGA-digital based on PID scheme	This method enhances the real time performance with concurrent computation and limited resources

6. Conclusions

In this paper, a novel method to enhance the performance of mechanical ventilator was investigated to support the medical treatment. There is an emergent need to carry out the aids since any trouble in this machine could cause the serious results. An overall framework of this design to yield the FPGA-based solution was introduced. Owing to the popularity of PID control, this scheme is also as powerful to discrete in digital expression. By using the hardware programming approach, this FPGA-accelerated control scheme provides a great performance for the respiratory characteristics. To verify the feasibility and effectiveness of proposed solution, the real-world test was established. From these tests, the system performance of proposed method guarantees stable execution, rapid response, and ease of implementation. Consequently, this technique could be applied in medical treatment procedure with low-cost.

Acknowledgments

We acknowledge Ho Chi Minh City University of Technology (HCMUT), VNU-HCM for supporting this study.

Disclosure statement

No potential conflict of interest was reported by the author(s).