Design and investigation of computation-in-memory based low power hybrid MTJ/CMOS logic gates

Abstract

Hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on the computation-in-memory (CIM) architecture are contemplated as the future generation of digital integrated circuits. It overcomes the limitations of von-Neumann architecture by offering solutions to problems such as memory wall and standby power dissipation. In this work, we have developed hybrid logic gates, such as AND/NAND, OR/NOR, and XOR/XNOR, for CIM architecture by integrating three terminal spin-Hall effect assisted spin transfer torque (SHE + STT) MTJs with standard CMOS. To write the MTJs an auto-write-stopping (AWS) circuit is adopted, whereas to perform the logic operations and produce the corresponding outputs, an improved sense amplifier circuit (ISA) is employed. All the hybrid logic gates are investigated for key performance indicators such as power, delay, device count, and power delay product (PDP). The results are compared with their conventional counterparts. The comparison reveals that the ISA + AWS-based hybrid gates dissipate 50.52% lower total power. The worst-case read delay of ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates are 27.41%, 13.4%, and 21.28% lower. Meanwhile, the reduction of read PDP (write PDP) is 47.64% (37.09%), 25.78% (36.29%), and 39.31% (35.48%) observed with ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates in comparison with the conventional counterparts. Hence the ISA + AWS gates are superior in terms of total power dissipation, worst read delay, and read/write PDP. Further, we have conducted Monte-Carlo simulations on all the logic circuits to study the parameter variations during fabrication.

Keywords:

• Magnetic tunnel junction
• spin-Hall effect
• spin transfer torque
• hybrid logic gates
• computation-in-memory

Reviewing Editor:

• Pham DT, University of Birmingham, United Kingdom

Subjects:

• Technology
• Engineering & Technology
• Electrical & Electronic Engineering
• Electronic Devices & Materials
• Technology

Disclosure statement

No potential conflict of interest was reported by the authors.

Author contributions

Prashanth Barla: Conceptualization (equal); Investigation (equal); Methodology (equal); Validation (equal); Writing – original draft (equal); Writing – review & editing (equal). Vinod Kumar Joshi: Conceptualization (equal); Methodology (equal); Supervision (equal); Validation (equal); Writing – review & editing (equal). Somashekara Bhat: Supervision (equal); Validation (equal).

Data availability statement

Data available on request from the authors.

Additional information

Notes on contributors

Prashanth Barla

Prashanth Barla received M.Tech. in Microelectronics & Control Systems from VTU, Belgaum, India and Ph.D. from MIT, Manipal, India. He is currently an Asst. Prof (Senior Sclae) with the Department of Computer Science & Engineering, at MIT, Manipal, India. His research interests include VLSI design, spintronics and its applications.

Vinod Kumar Joshi

Vinod Kumar Joshi received the M.Tech. degree from VIT University, Vellore, India, and the Ph.D. degree from Kumaun University, Nainital, India. He is currently an Associate Professor (Senior Scale) with the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal, India. His main research interests include spintronics based VLSI and logic-in-memory-based hybrid nonvolatile logic circuits for low-power applications.

Somashekara Bhat

Somashekara Bhat received the Ph.D. degree in the field of MEMS from IIT Madras, India. He is currently serving as a Professor with the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, India. His research interests include MEMS and electronics for biomedical applications.