Is thermal annealing a viable alternative for crystallisation in triethylsilylethynyl anthradithiophene organic transistors?

Figures & data

Figure 1. POM images for TESADT films annealed at T=(a) 100°C, (b) 105°C, (c) 110°C, (d) 115°C and (e) 120°C for 2 min. The white scale bar in panels (a–d) indicates 100 μm and (e) indicates 1 mm. The post-anneal crystalline domain size decreases for T>100°C with amorphous films obtained for T>115°C.

Figure 2. A POM study of domain size versus thermal anneal temperature T (horizontal axis) and time t (vertical axis) for T<100°C. The white scale bars indicate 1 mm. The optimal anneal conditions are T∼ 90°C for t∼ 3 min.

Figure 3. POM images of the best outcomes obtained using optimised (a) thermal- and (b) solvent-annealing processes. The images are composites of 25 smaller overlapping fields to enable the entire 10×10 mm area of the chip to be imaged (n.b., the tile-like contrast changes are an artefact). The white scale bars indicate 2 mm. (c–f) POM sequence showing the effect of alternating thermal (T) and solvent (S) anneals. The sequence begins with a solvent-annealed film (c), the remaining images are obtained after (d) a 2 min thermal anneal at 95°C, (e) a 2 min solvent anneal in dichloroethane vapour and (f) a second 2 min thermal anneal at 95°C. No visible change in the crystalline domain structure is obtained after the initial anneal confirming that both anneals drive towards the same crystal structure.

Figure 4. The drain current I_d versus drain voltage V_d for gate voltages from V_g=−50 V (top) to 0 V (bottom) in steps of 10 V for spin-coated TESADT transistors crystallised using (a) a 2 min solvent anneal in dichloroethane vapour, and (b) a 5 min thermal anneal at 90°C, and for (c and d) drop-cast TESADT transistors crystallised using (c) a 2 min solvent anneal in dichloroethane vapour, and (d) a 5 min thermal anneal at 90°C.

Figure 5. The drain current I_d versus gate voltage V_g for drain voltage V_d=−30 V for each of the four different TESADT transistors in Figure 4. The lines are measured transfer characteristics. The data points are extracted directly from Figure 4 to demonstrate correspondence between the transfer and source–drain characteristics for the four devices.

Table 1.  Key electrical performance parameters for the four types of TESADT thin-film transistors studied.

	Device 1	Device 2	Device 3	Device 4
Preparation	Spin–coated	Spin–coated	Drop–cast	Drop–cast
Anneal	Solvent	Thermal	Solvent	Thermal
Mobility(cm^2/Vs)	0.095		0.18
On–off ratio	82	3350	284	9030
Threshold Voltage(V)	−6	−35	−11	−39
Subthreshold swing(V/dec)	13.8	5.6	10.6	3.5

Figure 6. POM images (a) before and (b) after thermal annealing of a solvent-annealed TESADT film. The black and white arrows in (b) indicate cracks that developed during thermal annealing. (c) The field-effect mobility μ versus maximum anneal temperature for a TESADT transistor that underwent subsequent 2 min thermal anneals at T=30, 40, 50, 60, 70, 80 and 90°C, with electrical measurements performed at 25°C between each anneal. The initial point at T=25°C indicates a sample measured prior to any thermal annealing.