Control of subthreshold swing using an in situ PEALD nano-laminated IGZO/Al₂O₃ multi-channel structured TFT

Abstract

This study presents the development of multi-channel thin-film transistors (TFTs) using plasma-enhanced atomic layer deposition (PEALD) to stack layers of IGZO/Al₂O₃, with the number of stacking layers ranging from 1 to 10 (1S, 3S, 5S and 10S). To optimize the performance of the AM-LED display, the subthreshold swing (S·S) and mobility of each type of transistor, such as switching and driving transistors, were customized to meet specific requirements. The results show that as the number of stacking layers increased, the field-effect mobility (µ_FE) improved by 323% from 1.34 to 4.33 cm²/Vs, while S·S improved by 0.14 V/dec from 0.31 to 0.45 V/dec, with no variation in threshold voltage (V_th) and reliability. The study attributes the improvement in µ_FE and S·S to the formation of multiple electron transport paths as confirmed by a TCAD simulation showing an increase in current density. Overall, this study demonstrates the potential of PEALD in creating multi-channel TFTs with improved performance by customizing oxide semiconductor properties. This research may have important implications in the development of advanced electronic devices that rely on thin-film transistors, as it provides a new approach in enhancing the performance of these devices.

KEYWORDS:

• Atomic layer deposition (ALD)
• thin-film transistors (TFT)
• multi-channel TFT
• subthreshold swing control

1. Introduction

Active-matrix organic light emitting diode (AMOLED) displays have been industrialized over the last few decades. These displays provide low power consumption, high contrast ratios, and high resolutions compared with liquid crystal displays (LCD) [1–4]. In addition to OLEDs, LED-based displays are currently being used in high-resolution and flexible displays through micro-LEDs [5,6]. LED-based displays that employ a backplane for the active matrix consist of a switching thin-film transistor (S-TFT), driving TFT (D-TFT), and storage capacitor (C_st) to form a 2T1C cell [1,2]. S-TFT in the 2T1C cell is used to switch the device with high on/off ratio and facilitates current flow to C_st. D-TFT is used to detect the voltage level of the C_st and to provide current to the light emitting layer. The degree of brightness depends on the amount of this current.

AMOLED displays are widely implemented using low-temperature polycrystalline silicon (LTPS) [7]. However, power consumption issues are associated with LTPS TFTs due to current leakage problems. Recently, Apple Co., Ltd commercialized low-temperature polycrystalline silicon and oxide (LTPO) TFTs, which use LTPS and amorphous oxide semiconductors (AOSs) with low leakage current characteristics for D-TFTs and S-TFTs, respectively, to improve power consumption [4,8]. In addition, high-resolution displays require tens of hundreds of nano-amperes of current, a value that is lower than the previously required several micro amperes. The role of D-TFTs in active matrix displays such as AMOLED and AMLED is becoming important in achieving tens to hundreds of nano-amperes in low gradation regions. In order to control brightness in high-resolution displays, the behavior of D-TFT needs to be focused on driving in subthreshold rather than in the threshold region [9]. As a result, brightness adjustment in low power driving is more advantageous since it has a high SS value. However, since S·S is inherently increased by defects, TFTs with high SS can lead to deterioration of stability.

AOS TFT generally has a percolation behavior with a proportional relationship between the free carrier (n_free) and mobility above threshold voltage [10]. On the other hand, the behavior in subthreshold region is affected by trap carriers (n_trap) performing trap-limited conduction (TLC) [11]. In general, the S·S of AOS TFT is determined by the amount of n_trap by defects, and has a value of about 0.2 V/decade [12,13]. Likewise, the S·S value of LTPS TFT is determined depending on the grain boundary of the polycrystalline structure, and has a relatively high S·S value of 0.5 V/decade or more [14,15]. Therefore, if AOS TFTs with relatively high S·S can be developed without affecting stability, all oxide displays (excluding LTPSs) can be implemented in the AMOLED and AMLED industries.

In this work, we propose a method for controlling the µ_FE and S·S of oxide TFTs with nanoscale thin-film lamination through an in-situ plasma-enhanced atomic layer deposition (PEALD) process. A multi-channel TFT is manufactured according to the number of 2-nm-IGZO/3-nm-Al₂O₃ stacks (1S, 3S, 5S, and 10S). The formation of nanoscale thin-film laminations is confirmed through scanning transmission electron microscopy (STEM) and energy dispersive spectroscopy (EDS). The study revealed that as the number of IGZO/Al₂O₃ stacks increases, mobility and S·S also increase without any change in V_th and reliability. This trend is based on the total thickness of the IGZO/Al₂O₃ multi-channel layer structure, and a TCAD simulation can explain this tendency.

2. Experimental

Nano-scaled IGZO/Al₂O₃ stacked films were deposited through the PEALD process using O₂ plasma with [3-(dimethylamino)propyl] dimethyl indium, trimethyl gallium, diethyl zinc, and trimethyl aluminum as indium, gallium, zinc, and aluminum precursors, respectively. Deposition temperature and plasma power were 200°C and 100 W, respectively. IGZO was deposited at a rate of 2 nm per stack under a 12:1:1 PEALD cycle. The deposition rate of Al₂O₃ was 3 nm per stack. The number of IGZO/Al₂O₃ stacks was varied (1S, 3S, 5S, and 10S). We performed STEM and EDS analyses to verify the formation of a 2-nm-IGZO/3-nm-Al₂O₃ stacking layer. The ATLAS TCAD package (Silvaco, Inc.) was used to verify the change in the electrical properties of the multi-channel TFTs [16,17]. TCAD simulation was conducted based on the density of state (DOS) model, and the simulation parameters used are shown in Table S1.

Bottom-gate top-contact TFTs were fabricated by depositing the IGZO/Al₂O₃ stacking layers (1S, 3S, 5S, and 10S) onto a 100-nm-thick thermal SiO₂ and a heavily doped Si substrate as the gate dielectric and gate electrode, respectively. First, as-deposited stacking layers were patterned by photolithography and wet etching. Next, a 100-nm-thick indium tin oxide film was deposited as a source of drain electrodes by radio frequency magnetron sputtering and was patterned using photolithography and a lift-off process. The channel width and length were fixed at 40 and 20 µm, respectively. All devices were annealed at 350°C for 3 h in air. A Keithley 4200 semiconductor parameter analyzer was used to measure the electrical properties of the TFT devices under vacuum. Gate–source bias (V_GS) was swept from −10 to 10 V under V_DS = 0.1 V. PBS reliability was evaluated in a vacuum under the condition of 2 MV/cm (V_GS) for 3600 s.

3. Results and discussion

 Figure 1(a) shows the TFT structure in which IGZO is a semiconductor and Al₂O₃ is an insulator sequentially stacked to form the active layer. The thicknesses of IGZO and Al₂O₃ are 2 and 3 nm, respectively, and are deposited in nano-scaled thin-film lamination through an in-situ process using PEALD. We evaluated the optimal thicknesses of IGZO and Al₂O₃ in the 3S TFT, as shown in Figure S1. To compare the electrical characteristics of each device, a bottom-gate TFT with 2-nm-IGZO/3-nm-Al₂O₃ stacking layers (1S, 3S, 5S, and 10S) was evaluated. The performance of the 1S TFT that is 5 nm thick was V_th = 0.22 V, µ_FE = 1.34 cm²/Vs, and S·S = 0.31 V/dec. In contrast, the 10S TFTs of 50 nm or greater exhibited improved performance at V_th = 0.16 V, µ_FE = 4.33 cm²/Vs, and S·S = 0.45 V/dec. When the number of IGZO/Al₂O₃ stacking layers increased from 1S to 10S, the mobility and S·S were increased by 323% and 0.14 V/dec without any variation in V_th. Figure 1(b) shows the representative transfer curves for 1S, 3S, 5S, and 10S TFTs. The parameters are listed in Table 1. As the thickness of the IGZO/Al₂O₃ sequential stack increased, the µ_FE and SS gradually increased, and no change was observed in V_th. In general, previous studies have reported that as the thickness of the oxide semiconductor thin film increases, a negative V_th shift occurs or a non-switching property (i.e. conducting behavior) appears based on the directly proportional relationship between the carrier concentration and thickness [18,19]. However, experiments in this study revealed no change in V_th as the total thickness increased. Figure 1(c) shows the trend of electrical characteristics based on the number of stacking layers (1S, 3S, 5S, and 10S).

Figure 1. Schematic of (a) the stacked TFT with IGZO/Al₂O₃ using in situ PEALD (1S, 3S, 5S, and 10S TFTs), (b) representative transfer curve, and (c) trend of the electrical parameters of the devices based on the number of stacking layers.

Table 1. Device parameters (V_th, µ_FE and SS) for the 1S, 3S, 5S, and 10S TFTs.

Annealed at 350^oC	1S TFT	3S TFT	5S TFT	10S TFT
Vth [V]	0.22 ± 0.02	0.19 ± 0.05	0.13 ± 0.04	0.16 ± 0.03
μFE [cm^2/Vs]	1.34 ± 0.21	2.40 ± 0.19	2.94 ± 0.10	4.33 ± 0.08
S·S [V/decade]	0.31 ± 0.01	0.31 ± 0.02	0.36 ± 0.02	0.45 ± 0.02

STEM analysis was conducted to confirm nano-scaled IGZO/Al₂O₃ thin film lamination through in situ PEALD. Figure 2(a) shows that the laminated thin film of the 10-stack 2-nm-IGZO/3-nm-Al₂O₃ deposited through in situ PEALD was well-formed. STEM analysis confirmed that Al₂O₃ of 3.45 nm and IGZO thin films of 2.22 nm were well-separated and formed, and the total thickness of the 10-stack IGZO/Al₂O₃ thin film was 56.5 nm. From the EDS analysis presented in Figure 2(b), we confirmed that the layers of IGZO and Al₂O₃ were well-classified by mapping In and Al elements. In addition, the distribution of In, Ga, Zn, and Al components through vertical line scanning (A–A′) also confirmed that the nano-scaled IGZO/Al₂O₃ was well separated, as shown in Figure 2(c). Therefore, it is thought that the effective formation of IGZO/Al₂O₃ through in situ PEALD is irrelevant to the degradation in the device’s performance.

Figure 2. (a) STEM image, (b) EDS mapping image (2-D) of Al and In, (c) vertical EDS line scan (1-D) of Al, In, Ga and Zn in a 10-stack IGZO/Al₂O₃ layer.

A TCAD simulation was conducted to confirm the device performance tendencies (increase in µ_FE and S·S) based on the IGZO/Al₂O₃ thickness in the multi-channel TFTs. Simulations of the 1S, 3S, 5S, and 10S TFTs confirmed changes in device performance based on the number of stacking layers, as shown in Figure S2. Figure 3(a) shows the 2D distribution of the total current density of the multi-channel TFTs in the driving state (V_GS = 10 V, V_DS = 0.1 V). A current path was formed on all layers of IGZO in the 1S, 3S, 5S, and 10S TFTs. Figure 3(b) shows that the vertical distribution was confirmed, which in turn enabled a comparison of the current density values based on the number of stacking layers. In the first front IGZO layer, the current density peak in the 1S, 3S, 5S, and 10S TFTs was 85.5, 93.7, 125.2, and 210.8 A/cm², respectively. This means that mobility was increased by an increase in the current density only in the first front IGZO layer by means of the nano-scaled lamination process. In addition, excluding the first front IGZO layer, the log scale of the current density showed that an additional current path was formed with a relatively lower current density (<10 A/cm²), as shown in the inset of Figure 3(b). This was not only due to the increasing active thickness but was also derived from the effect of the multi-channel TFT structure.

Figure 3. (a) 2-D and (b) 1-D distributions of the simulated current density under the operational state (V_GS: 10 V, V_DS: 0.1 V) based on multi-channel TFT (1S, 3S, 5S and 10S TFTs).

To verify what caused the different trend from previous reports based on the increase in active layer thickness, the vertical band alignment (B–B′) of the gate insulator and active layer was simulated under the operational state of V_GS = 10 V and V_DS = 0.1 V for the 1S, 3S, 5S, and 10S TFTs, as shown in Figure 4. In general, most of the applied electric field in the metal insulator semiconductor (MIS) capacitor is assigned to the insulator layer to form the capacitance. In the semiconductor layer, band bending occurs depending on the influence of the carrier concentration or thickness [20]. The band bending occurs primarily near the interface between the gate insulator and active layer, and the electric field is not applied to the entire semiconductor layer. Because semiconductors (IGZO) and insulators (Al₂O₃) are sequentially stacked, this may be different from applying an electric field to the normal MIS structure. When the gate bias (V_GS) is applied, the role of Al₂O₃ in the multilayer of 2-nm-IGZO/3-nm-Al₂O₃ is to enhance the degree of band bending of IGZO. In the 1S, 3S, 5S, and 10S TFTs, the total band bending values of IGZO were 0.03, 0.06, 0.09, and 0.11 V, respectively, and the total voltage applied to Al₂O₃ was 0.00, 0.04, 0.04, and 0.41 V at the enlarged conduction band, as shown in Figure 4(a–d) and as listed in Table 2. Table 2 also lists the decompositions of applied potential on the G.I (SiO₂), IGZO, and Al₂O₃ layers under the operational state. Accordingly, the band bending energy of the first front IGZO layer gradually increased to 0.03, 0.04, 0.04, and 0.05 eV in the 1S, 3S, 5S, and 10S TFTs, respectively. Therefore, the increase in mobility based on the increase in the number of stacks was primarily due to the enhancement of band bending of the first front IGZO layer by the multi-stacked Al₂O₃ layer.

Figure 4. Energy band and enlarged conduction band edge in the gate insulator (SiO₂) and IGZO/Al₂O₃ under the operational state (V_GS: 10 V, V_DS: 0.1 V) for (a) 1S, (b) 3S, (c) 5S, and (d) 10S TFTs.

Table 2. Potential decomposition under the operational state (V_GS: 10 V and V_DS: 0.1 V) in the gate insulator (SiO₂) and multilayer (IGZO and Al₂O₃).

VGS: 10 V	1S TFT	3S TFT	5S TFT	10S TFT
$V_{\text{Si}{\text{O}}_2}$ (V)	9.97	9.90	9.87	9.48
VIGZO (V)	0.03	0.06	0.09	0.11
$V_{\text{A}{\text{l}}_2{\text{O}}_3}$ (V)	0.00	0.04	0.04	0.41

In addition, TCAD shows the formation of multiple electron channels as well as the bending enhancement of the first front IGZO layer through the results of simulated band bending and current density. Compared to the first channel capable of percolation conduction behavior, multiple channels with less band banding and low electron density may carry out TLC behavior. This means that the subthreshold region may have been affected by multi-channel formation other than enhancement of the first front IGZO layer. This is because the number of electrons performing TLC behavior in the subthreshold region switching on and off has increased. Therefore, employing a multi-channel structured TFT can control the device performance (mobility and S·S) of the oxide TFT.

To identify the mechanism for modulation of electrical characteristics through IGZO and Al₂O₃ nano-scaled lamination, an evaluation of PBS reliability was conducted. Results showed that increasing the number of stacks did not affect PBS reliability and that the ΔV_th had similar values regardless of the number of stacking layers, as shown in Figure 5. The V_th shift value was 2.08 ± 0.15, 2.57 ± 0.21, 2.40 ± 0.16, and 1.98 ± 0.25 V for the 1S, 3S, 5S, and 10S TFTs, respectively. These results were derived from the fact that the electron trapping events attributed to the applied gate bias stress occurred only at the interface between the G.I and the first front IGZO layer (main channel). We verified that the device performance based on a multi-channel structure could be controlled without affecting reliability. In short, our proposed IGZO/Al₂O₃ multi-channel TFT structure with band bending enhancement of the main channel and multi-channel formation may be able to control device performance without affecting PBS reliability.

Figure 5. Changes in V_th with stress time under PBS evaluation (V_GS: 2 MV/cm, time: 3600 s).

4. Conclusion

We present the multi-channel TFTs to control the subthreshold swing and mobility. Multi-channel TFTs were fabricated based on the number of 2-nm-IGZO/3-nm-Al₂O₃ stacking layers (1S, 3S, 5S, and 10S) by nano-scaled thin-film lamination using an in situ PEALD process. In 10S IGZO/Al₂O₃, mobility was increased by 323%, while the S·S was increased by 0.14 V/dec without any variation in V_th as compared with the 1S TFT. A well-separated multilayer IGZO/Al₂O₃ formation was confirmed through STEM and EDS analyses. The cause of this tendency based on the thickness of the multi-channel structure TFT was determined through a TCAD simulation. The Al₂O₃ layer as an insulator in the multi-channel layer had an electric field formed by a gate bias as well as a gate insulator (SiO₂), which enhanced the band bending of IGZO. The first front IGZO layer (main channel) exhibited a higher current density by enhanced band bending. Multiple electron transport also led to an increase in S·S. Finally, we verified that the device’s performance could be intentionally modulated without affecting reliability. Multi-channel engineering in oxide semiconductors is anticipated to become the significant technology to manipulate current-driven operation for various active matrix displays such as AMOLED and AMLED.

Acknowledgement

This work was supported by the Industry Technology R&D Program [grant number 20006400] funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Won-Bum Lee

Won-Bum Lee received a B.S. degree from the Division of Materials Science and Engineering of Hanyang University, Seoul, South Korea. His research work has been focused on thin-film transistors based on metal oxide materials.

Yoon-Seo Kim

Yoon-Seo Kim received his B.S. degree from the Division of Materials Science and Engineering of Hanyang University, Seoul, South Korea. His research work has been focused on thin-film transistors based on metal oxide materials.

Jin-Seong Park

Jin-Seong Park received his Ph.D. degree from the Department of Materials Science and Engineering of KAIST, Daejeon, South Korea, in 2002. He then worked at Roy Gordon’s Laboratory in Harvard, USA as a postdoctoral associate. Since 2013, he has been a Professor at the Division of Materials Science and Engineering of Hanyang University, Seoul, South Korea. Awards he received include the Merck Young Scientist Award (2014) and Merck Special Award in ALD Materials and Process (2021).