A low-power metal–oxide scan driver circuit outputting non-overlapping pulses with DC power-supplied buffer

Abstract

This paper proposes a novel metal–oxide (MOx) thin-film transistors (TFT)-based scan driver circuit with a DC power-supplied buffer. This circuit has two parts: a ‘carry generation block (CGB)’ and an ‘output generation block (OGB).’ The CGB generates a carry pulse by the bootstrapping effect of pull-up TFT with the aid of clock signal; clock-supplied bootstrapping. Then the OGB is controlled by the carry pulse, and the output pulse is generated by the bootstrapping effect of pull-up buffer TFT with DC power supply; DC-supplied bootstrapping. In the proposed circuit, the pull-up TFT in CGB does not need to have wide dimensions because the carry signal is separated from the large capacitive load in the pixel area. Accordingly, the capacitive load of the clock signal is significantly reduced, and the dynamic power consumption associated with clock toggling decreases remarkably compared with the conventional scan driver circuit that uses the clock-supplied bootstrapping for the wide output buffer TFT. In addition, a bootstrapping inverter in OGB makes the output pulse width the same as the clock-high duration, preventing the output pulses from overlapping, which is required for most of the organic light-emitting diode (OLED) pixel circuits with in-pixel compensation.

KEYWORDS:

• Organic light-emitting diode (OLED) display
• scan driver circuit
• double-gate (DG) metal-oxide (MOx) thin-film transistor (TFT)
• depletion mode
• low-power consumption

Introduction

Metal-oxide (MOx) thin-film transistors (TFT), compared to low-temperature polycrystalline silicon (LTPS) TFT, do not require a burdensome excimer laser process and have exceptionally low leakage current levels. Hence, recently, extensive research has been underway to apply MOx TFTs to the backplane of mobile organic light-emitting diode (OLED) displays to achieve low power consumption by adopting low refresh rate driving and cost savings in manufacturing. Most scan driver circuits with MOx TFTs generate output pulse by connecting the clock signal to the very wide pull-up buffer TFT T6, as indicated in Figure 1 [1–3]. Although this configuration is easy to implement as a circuit capable of high-speed operation through the clock-supplied bootstrapping effect, however, the power consumption increases due to continuous charging and discharging of the large parasitic capacitance C_par2 of the pull-up buffer TFT. Thus, recently, scan driver circuits utilizing a DC power-supplied output buffer have also been proposed [4–6]. It can significantly reduce power consumption because no charging and discharging occurs in the large parasitic capacitance of the wide pull-up buffer TFT. However, it is difficult to generate a steep output pulse, and due to the overlap problem of the output pulses, it cannot also be used in normal OLED pixel circuits where the data voltage applying time and the threshold voltage (V_TH) extraction time overlap during compensation. As a result, it reduces the versatility of the circuit, suggesting the need to develop improved scan driver circuits to solve these problems.

Figure 1. Circuit diagram of conventional MOx TFT scan driver circuit adopting clock-supplied bootstrapping

This work proposes a new scan driver circuit consisting of MOx TFTs that enables operation with low power consumption by generating the output pulse using a DC power-supplied buffer and operates even for the depletion mode TFTs. Furthermore, the circuit is configured with double-gate (DG) MOx TFTs, enabling high-speed operation of the circuit. The issue of overlapping output pulses, which usually occurs in scan driver circuits using a DC power-supplied buffer, has been solved, enhancing its versatility for typical OLED pixel circuits.

Proposed scan driver circuit with DC power-supplied buffer

Figure 2 shows the structure and timing diagram of the proposed circuit. This circuit comprises two main parts, ‘the carry generation block (CGB),’ and ‘output generation block (OGB).’ The proposed circuit produces the Carry[n] pulse in the CGB and the Out[n] pulse in the OGB. Two non-overlapping clock signals are used, as demonstrated in Figure 2 (c) and the Carry[n] pulse has the same pulse width as that of the clock signals connected to the pull-up TFT T8 of CGB. Therefore, the Carry[n] pulse turns on the pull-up buffer TFT T15 in the OGB for less than one horizontal-line time (1H), and the first prerequisites for the generation of non-overlapping output pulses can be satisfied even with the DC power-supplied buffer. The bootstrapping inverter controls the QB2[n] node according to Carry[n], so the pull-down buffer T16 is turned on as soon as T15 is turned off. In this way, all conditions for non-overlapping output pulse generation are met in the proposed circuit. However, the pull-down buffer TFT in the previous scan driver circuits with DC power-supplied buffer [4–6] is controlled by the other clock signal or the output pulse of the next stage; thus, the output pulse overlapping occurs between the current stage and the next stage.

Figure 2. (a) Circuit diagram of the proposed MOx 16T-2C scan driver circuit, (b) the block diagram of the scan driver with three consecutive stages, and (c) the timing diagram of the operation

Operation sequence of circuit

• Low-voltage holding period

This period is indicated as (1) in Figure 2 (c). In Figure 2 (a), Carry[n] and Out[n] keep VGL2 and VGL1 levels, respectively, regardless of CK1 and CK2 swings as long as Carry[n-1] remains at VGL2 level. VGL2 level is lower than VGL1 level. The gate node of T6 is charged up because T3 is turned on periodically by CK2 resulting in normally high QB1[n] voltage. Accordingly, T2 and T9 are also turned on by high QB1[n] voltage. Carry[n], P[n] and Q1[n] nodes are discharged to the VGL2 level through T9, T2, and T5 in order. This keeps T8 turned off, preventing the generation of carrying [n] pulses against the CK1 swing. The pull-up buffer T15 is also turned off because the Q2[n] voltage is VGL2 following the Carry[n]. Meanwhile, T12 and T14 are turned off by the low Carry[n] voltage; thus, QB2[n] voltage is kept high. Consequently, T16 is turned on, and the Out[n] node is kept at VGL1.

• Pre-charging period

At the beginning of this period, Carry[n-1] and CK2 voltages rise from VGL2 to VGH, and QB2[n-1] voltage falls concurrently. So, T1 is turned on, making P[n] and Q1[n] node voltages high, whereas QB1[n] is pulled down because T4 is turned on and T6 is turned off. Both T2 and T9 are turned off by the VGL2 level of the QB1[n] node, so the voltage of the Q1[n] node is kept high enough. Due to the high Q1[n] voltage, T8 is also turned on; however, since the voltage of CK1 is VGL2, the Carry[n] voltage remains at VGL2. Accordingly, Out[n] does not change and maintains the VGL1 level.

• Bootstrapping and pulse-generating period

As Carry[n-1] voltage falls to VGL2, T1 is turned off, causing P[n] and Q1[n] nodes to enter a floating state. Then, the voltage of CK1 rises from VGL2 to VGH, and thus the Q1[n] node is bootstrapped by C1 and T8, generating the Carry[n] pulse. The Carry[n] pulse turns on T7, pulling the gate node of T6 down to VGL2 via the QB1[n] node. Consequently, T6 remains turned off while T4 is turned on, allowing QB1[n] voltage to maintain a low voltage. Therefore, T9 is turned off, and a stable VGH level of the Carry[n] pulse is maintained.

High Carry[n] voltage results in low QB2[n] voltage by the bootstrapping inverter. Thus, T16 is turned off and the voltage rise at the Q2[n] node through T10 leads to the second bootstrapping effect by C2 and T15. We call this DC-supplied bootstrapping to distinguish it from the first bootstrapping using the clock signal, which may be called clock-supplied bootstrapping. Figure 3 displays how the DC-supplied bootstrapping occurs in the proposed circuit. When the Carry[n] pulse is generated, Q2[n] node voltage also rises quickly, as expressed in Figure 3 (a). However, the Out[n] node voltage rises much slower than the Q2[n] node due to the large capacitive load. Therefore, a positive gate-to-source bias (V_GS) is set on T15, which is sufficient to turn on T15. Then T15 begins to pull up Out[n], but the Q2[n] voltage rises more quickly by the voltage transfer through T10. As the Q2[n] voltage rises further, T10 is turned off, and the Q2[n] node enters the floating state. Then Q2[n] node is boosted by the capacitive coupling with Out[n] voltage rise through C2, as represented in Figure 3 (b). Consequently, the Q2[n] node voltage can rise higher than VGH, and the Out[n] can reach VGH even though T15 has a positive V_TH. To maximize the DC-supplied bootstrapping effect and minimize the rise time of Out[n], the sizes of T10 and T15 as well as C2 should be optimized depending on the load capacitance.

• Discharging Period

Figure 3. Operation principle of the DC-supplied bootstrapping: (a) Q2[n] node is charged quickly, while Out[n] voltage rises slowly due to large load capacitance. (b) Subsequent Out[n] voltage rise causes bootstrapping at the Q2[n] node.

As the Carry[n] pulse falls to VGL2 following the CK1 signal, T7 and T15 are turned off. Simultaneously, T12 and T14 in the bootstrapping inverter are turned off and then the bootstrapping effect of T13 quickly pulls QB2[n] up to VGH, turning on T16 strongly and pulling down Out[n] as fast as possible. The Out[n] voltage drops, following the CK1 voltage drop, regardless of the CK2 signal. Therefore, output pulse overlap between adjacent stages can be avoided. Then as the CK2 signal rises to VGH, T3 is turned on, charging the gate node of T6 to a high voltage. Consequently, the QB1[n] node is pulled up by T6, which turns on T2 and T9, pulling down the P[n], Q1[n], and Carry[n] nodes during the low-voltage holding period. Since P[n] node voltage is VGL2, T4 is turned off, and stable high voltage is maintained at QB1[n]. The stable high voltages at QB1[n] and QB2[n] nodes ensure stable low voltage levels of VGL2 and VGL1 at Carry[n] and Out[n], respectively.

Results and discussion

The performance, operation margin, and power consumption of the proposed 16T-2C scan driver circuit were verified using SmartSpice of Silvaco Inc. Figure 4 describes the measured transfer characteristics and SPICE simulation models of single-gate (SG) TFT and double-gate (DG) MOx TFT when the drain-to-source bias (V_DS) is 0.1 V or 10 V. The field-effect mobility of the SG MOx TFT is 9.6 cm²/V·s and the DG MOx TFT is 14.3 cm²/V·s respectively. RPI poly-silicon TFT model (Level = 36) was used for the SG TFT, and the Leti-UTSOI MOSFET model (Level = 76) was used for the DG TFT, respectively.  When measuring the characteristics in Figure 4 (b), the top and bottom gate electrodes had the same bias, which is the so-called gate-synchronized configuration.

Figure 4. Measured transfer characteristics of n-type MOx TFTs and their SPICE model characteristics: (a) single-gate TFT and (b) double-gate TFT with gate-synchronized configuration

To reduce the capacitive load of the clock signal, the pull-up TFT T8 in CGB has the SG structure, whereas all other TFTs have the DG structure. The design parameters of the proposed scan driver circuit are listed in Table 1. Specifically, to generate a steep output pulse, the pull-up buffer TFT T15 has the largest width of 400 μm. In contrast, to reduce the power consumption related to the capacitive load of the clock signals, T3 and T8 have very small channel widths of 3 and 10 μm, respectively. Figure 5 illustrates the resistance and capacitance model of the OLED display panel used in the SPICE simulation. C_{Drvr_Ckt} represents the capacitive load of clock signal, originating from the gate electrodes of the TFTs in the entire scan driver circuit. It varies significantly depending on the circuit structure and the number of stages. It may have a very large value if the clock signals are connected to wide buffer TFTs, as in the case of reference 3. However, it may have a very small value if the clock signals are connected to small TFTs, as in reference 4 and the current circuit. On the other hand, other load conditions have typical values according to the display resolution and panel size. For instance, in a six-inch OLED display with 3k vertical resolution, the load resistance and capacitance attached to the Out[n] node were set as R_Load = 2 kΩ and C_Load = 25 pF, respectively. Then, the resistance and capacitance of the clock signal line were set as R_{Clk_Line} = 500 Ω and C_{Clk_Line} = 30 pF, respectively.

Figure 5. Capacitance and resistance model of the six-inch OLED display panel used in the SPICE simulation

Table 1. Design parameters of the proposed 16T-2C scan driver circuit.

Parameter	Value
VGH	7 V
VGL1	−8 V
VGL2	−11 V
CK1, 2	7 V/−11 V
W/L of T1, T2, T3, T5, T11, T12	3/3 μm
W/L of T4, T6	4/3 μm
W/L of T9	5/3 μm
W/L of T7, T13, T14	8/3 μm
W/L of T8	10/3 μm
W/L of T10	30/3 μm
W/L of T16	160/3 μm
W/L of T15	400/3 μm
C1	150 fF
C2	100 fF
RLoad	2 kΩ
Cload	25 pF
RCllk_Line	500 Ω
CCllk_Line	30 pF

Ten stages connected in a cascade were used for the simulation. Assuming a 3k vertical resolution and a 60 Hz refresh rate, the clock frequency is 90 kHz, which corresponds to an operation frequency of 180 kHz because the output pulses occur every 1/180,000 s. The pulse width of the clock signals is 5 μs.

Figure 6 presents the simulation results of the proposed 16T-2C scan driver circuit for various V_TH values, implying that the circuit works without output pulse overlap nor distortion for the TFT’s V_TH range from −3 V to 3  V. In particular, Figure 6 (b) reveals that when the circuit operates with a positive V_TH value within the range of 0 V ≤ V_TH ≤ 3 V, Q2[n] voltage rises above VGH due to the DC-supplied bootstrapping effect of T15 and C2. Contrarily, when the circuit operates with a negative V_TH value within the range of −3 V ≤ V_TH < 0 V, T10 remains turned on, preventing the Q2[n] from floating. Consequently, the bootstrapping effect does not occur. However, in this case, since V_TH is negative, the Out[n] pulse can rise to the VGH. In this circuit, the DC-supplied bootstrapping effect is needed only for the enhancement mode TFTs, which is successfully implemented.

Figure 6. SPICE simulation results of output waveforms with V_TH variation at 180 kHz operating frequency. (a) Output voltage waveforms from the 2nd to the 7th stages and (b) Voltage waveforms of Out[n] and Q2[n] nodes in the 4th stage.

The typical V_TH of a MOx TFT was controlled between 0 and 1 V. When V_TH = 1 V, the rise and fall times of the output pulse were measured as 387 and 338 ns, respectively, as indicated in Figure 7. They decreased to 342 and 313 ns, respectively, as V_TH decreased to 0 V. The output pulses of the proposed circuit were steep enough to drive an OLED display with 3k vertical resolution at a refresh rate of 60 Hz or higher.

Figure 7. Simulation results of the rise and fall times for various V_TH values

We calculated the power consumption of the scan driver circuit composed of 3k stages. At every moment, most stages maintain Out[n] = VGL1. Only one stage had a high-voltage pulse output. So, we considered two different cases of operation. In both cases, we used 10 stages of the scan driver circuit for power calculation by SPICE simulation. First, all 10 stages maintained Out[n] = VGL1 even though the clock signals were supplied continuously. The power consumption obtained in this case (P_{10_Low}) was multiplied by 299 to produce the dynamic power consumption of 2990 stages. This was directly related to C_{Drvr_Ckt}. Then the power consumption of the other 10 stages in which one stage had Out[n] = VGH pulse (P10_Pulse) was calculated by SPICE simulation, which included the static power dissipated in the bootstrapping inverter (∼ 0.5 mW) because the pull-down TFTs T12 and T14 in the bootstrapping inverter were turned on only when Carry[n] = VGH. The power consumption of these ten stages also involved the dynamic power consumption related to charging and discharging of C_Load, which was 1.01 mW because P = CV²f = 25 pF × (15 V)² × 180 kHz. Finally, the dynamic power consumption associated with charging and discharging of C_{Clk_Line} (P_{Clk_Line}) was added to these two power components, 299 times P_{10_Low} and P_{10_Pulse}. The total power consumption obtained by this means is detailed in Figure 8 and Table 2.

Figure 8. Power consumption of the proposed circuit driven at 60 Hz or 120 Hz refresh rate for various V_TH values

Table 2. Comparison of the power consumption between the proposed circuit and previous circuits.

	Ref. [3]	Ref. [4]	This Work
Size of TFTs connected to the clock signal	6/3 μm (T6c),340/3 μm (T6)	10/3 μm (T13)	3/3 μm (T3),10/3 μm (T8)
Output buffer TFT size	340/3 μm (T6),200/3 μm (T7)	1600/3 μm (T17),500/3 μm (T18)	400/3 μm (T15),160/3 μm (T16)
Operating frequency	180 kHz	180 kHz	180 kHz
Clock voltage swing	15 V	18 V	18 V
Output voltage swing	15 V	15 V	15 V
Number of stages	3000	3000	3000
Rise/Fall times	397/347 ns	417/376 ns	387/338 ns
Power due to CClk_Line (PClk_Line)	1.22 mW	1.75 mW	1.75 mW
Power of 10 stages with Out[n] = Low (P10_Low)	20.8 μW	1.17 μW	0.94 μW
Power of 10 stages with Out[n] = Pulse (P10_Pulse)	2.31 mW	1.40 mW	1.80 mW
Total power consumption	9.75 mW	3.50 mW	3.83 mW

Figure 8 shows the total power consumption of 3k stages for various V_TH values when driven at 60 Hz or 120 Hz refresh rate. For the 120 Hz, the pulse width of the clock signals was set to 2.5 μs in the simulation. For V_TH = 1 V, the power consumption was as low as 3.83 mW at 60 Hz and 5.35 mW at 120 Hz, respectively. It decreased slightly as V_TH increased. However, it increased anomalously as V_TH decreased due to the leakage current in CGB and the bootstrapping inverter. The proposed circuit can significantly reduce C_{Drvr_Ckt} by employing the DC-supplied bootstrapping for the output buffer and thus the dynamic power consumption has remarkably decreased compared with the conventional scan driver circuit that adopts the clock-supplied bootstrapping [3].

The proposed scan driver circuit’s power consumption was compared with the previous circuits, as specified in Table 2. Most operating conditions and load conditions of the three circuits were set similarly to facilitate power consumption comparison. The sizes of the output buffer TFTs were optimized to have similar rise and fall times. The P_{10_Low} of the circuit with clock-supplied bootstrapping buffer in reference 3 is about 20 times larger than those of the circuits with DC-supplied buffer in reference 4 and this paper. In the circuits with a DC-supplied buffer, the dynamic power consumption associated with C_{Drvr_Ckt} (i.e. 299 times P_{10_Low}) is about one-tenth of the total power consumption, which is the sum of P_{Clk_Line}, P_{10_Pulse,} and 299 times P_{10_Low}. However, the circuit with a clock-supplied bootstrapping buffer in reference 3 was about 64% of the total power consumption. The P_{10_Pulse} of the circuit in reference 3 and our circuit was higher than that of the circuit in reference 4 because the former two circuits had static current flow when the output was high, whereas the latter circuit did not. The total power consumption of the proposed scan driver circuit decreased by below half compared with the previous circuit in reference 3. In addition, our circuit did not have an output pulse overlap problem in the circuit, as in reference 4.

Conclusions

We reported a new MOx TFT-based 16T-2C scan driver circuit that can reduce power consumption by connecting the DC power supply to the large buffer TFT instead of the clock signal. In addition, the problem of output pulse overlap commonly encountered in conventional circuits using DC power-supplied buffer TFT has been successfully solved by incorporating the NMOS bootstrapping inverter. The proposed circuit adopts the DG TFTs where possible to enable high-speed operation. The SPICE simulation results show that the circuit operates for 3k resolution at a refresh rate of 60 Hz or higher within the range of −3 V ≤ V_TH ≤ 3 V. The power consumption of the proposed circuit has been reduced by connecting the clock signals only to small TFTs, T3 and T8 of which W/L is 3 μm/3 μm and 10 μm/3 μm, respectively. When TFT’s V_TH = 1 V, the power consumption of 3k stages calculated by SPICE simulation is as low as 3.83 and 5.35 mW at the refresh rate of 60 and 120 Hz, respectively.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the Technology Innovation Program funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) [grant number 20016317], On-Panel Circuit Integration and Driving System Technology for 1270 ppi Low-Power OLED Display Based on Oxide Semiconductor.

Notes on contributors

HyeongMin Kim

HyeongMin Kim received his B.S. degree in electronics engineering from Konkuk University, Seoul, Korea, in 2023. He is now an M.S. candidate at the same university. His research interests include the design of LTPS/oxide thin-film transistor circuits for AMOLED displays.

JungSuk Oh

JungSuk Oh received his B.S. degree in electronics engineering from Konkuk University, Seoul, Korea, in 2022. He is now an M.S. candidate at the same university. His research interests include the design of LTPS/oxide thin-film transistor circuits for AMOLED displays.

YiKyoung You

YiKyoung You received her B.S. degree in electronics engineering from Konkuk University, Seoul, Korea, in 2020. She is currently working toward a Ph.D. degree at the same university. Her research interests include LTPS/oxide thin-film transistor circuit design for AMOLED displays.

SangWoon Lee

SangWoon Lee received his B.S. degree in electronics engineering from Konkuk University, Seoul, Korea, in 2023. He is now an M.S. candidate at the same university. His research interests include the design of LTPS/oxide thin-film transistor circuits for AMOLED displays.

KeeChan Park

KeeChan Park received his B.S., M.S., and Ph.D. degrees in electrical engineering from the Seoul National University, Seoul, Korea, in 1997, 1999, and 2003, respectively. He worked for Samsung Electronics as a senior engineer from 2003 to 2007. Since 2007, he has been a professor at Konkuk University, Seoul, Korea. His research area includes display panel designs, circuit integration using TFTs, and device characterization.