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Original Articles

Is thermal annealing a viable alternative for crystallisation in triethylsilylethynyl anthradithiophene organic transistors?

, , , , , & show all
Pages 7-14 | Received 07 Dec 2013, Accepted 05 Apr 2014, Published online: 05 May 2014

Abstract

Triethylsilylethynyl anthradithiophene (TESADT) holds considerable promise for organic transistor applications due to the high electrical mobilities attained by post-deposition crystallisation using solvent vapour annealing. We have studied thermal annealing as an alternative route to post-deposition crystallisation of TESADT films. Thermal annealing initially appears promising, producing mm-sized crystal domains, but poor electrical performance is obtained, which we attribute to a combination of crack formation and potentially also a structural transition during the anneal process. We also find that illumination has a significant positive effect on crystallisation, possibly due to an optically induced enhancement in molecular mobility during annealing. This suggests that further studies of how solvent exposure, heat, substrate surface properties and particularly light exposure influence the ordering kinetics of TESADT are warranted.

1. Introduction

Improved electrical performance is an important goal in the development of organic field-effect transistors. Gains are achieved through better molecular ordering in the organic thin film forming the transistor's conducting channel.[Citation1,Citation2] Carrier mobilities exceeding 0.1 cm2/Vs are routinely obtained using liquid-crystalline semiconducting polymer films, e.g. regioregular polythiophenes,[Citation3] or crystalline small-molecule organics, e.g. pentacene.[Citation4,Citation5] The quest for optimal molecular packing has driven the development of functionalised acenes [Citation6–8] and functionalised acenedithiophenes,[Citation9–12] with triethylsilylethynyl anthradithiophene (TESADT) [Citation13] showing particular promise for applications. TESADT is readily solution processed into thin films. These films are amorphous upon deposition and easily crystallised by brief exposure to organic solvent vapour, giving saturation electrical mobilities ∼0.1 cm2/Vs.[Citation14] TESADT films can be patterned [Citation15] using a polydimethylsiloxane stamp prior to annealing or by masked UV illumination during annealing.

Despite TESADT’s effectiveness, solvent annealing presents some practical issues for reliable large-area processing; for example, precise areal control over solvent exposure ‘dose’ is difficult. Thermal annealing is commonly used to improve crystallinity in the fabrication of devices using inorganic semiconductors, e.g. Si.[Citation16,Citation17] Such thermal processes are more readily controlled and may provide a viable alternative to solvent annealing for organic devices. We investigated this possibility, performing a study of the comparative efficacy of thermal and solvent annealing for improving the order and electrical properties of TESADT films. Recent work has also shown that TESADT transistors with high electrical mobilities can be obtained by vacuum ageing [Citation18] and low-temperature casting [Citation19,Citation20] of TESADT films. We put our results into context with these novel routes to higher performance TESADT transistors, further highlighting the important and complex role that solvent, heat, light and substrate surface play in determining the electronic properties of TESADT films.

2. Materials and methods

TESADT was synthesised as described previously [Citation9] and a 3% w/w solution in toluene was prepared for spin-coating or drop-casting onto prefabricated, bottom-contact transistor structures. The transistor structures consist of a 10 mm square, heavily doped Si substrate with 450 nm thermal oxide and six sets of 4 nm Ti:40 nm Au source/drain contacts deposited using standard photolithographic techniques. The resulting transistor structures have channel width W=1000 μm, channel length L=100 μm and a specific gate–channel capacitance C=7.7±0.5 nF/cm2. Substrates were washed in acetone and isopropanol, and O2 plasma cleaned prior to TESADT deposition. Spin-coated films were spun at 5000 rpm for 60 s followed by room temperature vacuum desiccation for 30 min to remove residual solvent. We deposited drop-cast films by touching a 10 μL glass capillary containing TESADT solution to the substrate surface. The capillary was withdrawn once the solution had spread radially to cover a given transistor structure. The results presented come from a study of over a hundred films/devices from five separately synthesised batches of TESADT.

Solvent annealing was achieved by a 2 min exposure to dichloroethane vapour.[Citation14] Thermal annealing was performed by placing the substrate on a hotplate at a specific temperature T for a time t. Polarised optical microscopy (POM) was primarily used to assess crystallinity due to its better ability to demonstrate crystal domain size effects and the large number of samples involved in the study. Shallow-angle X-ray diffraction measurements were used to confirm packing structures in cases where this might deviate from known structures in the literature. Electrical measurements were performed in a light-tight, N2 filled, ground-shielded probe station at room temperature. Drain and gate biases Vd and Vg were applied using Keithley 236 source–measure units; these also measure the drain Id and gate Ig currents. The source current Is is measured using a Keithley 6517A electrometer, with the source held at ground.

3. Results and discussion

3.1. Crystallisation of TESADT thin films using thermal annealing

We first determined the upper temperature limit for thermal annealing. The known bulk melting temperature of TESADT is 151°C.[Citation13] However, additional structural phase transitions are commonly observed in differential scanning calorimetry studies.[Citation18,Citation20,Citation21] Additionally and in particular, a recent study using variable temperature wide-angle X-ray scattering revealed the presence of four polymorphs: one amorphous phase, denoted a, and three crystalline phases, denoted α, β and γ.[Citation20] The α-phase is obtained from low-temperature casting of the film, the β-phase is obtained at high temperatures , and the γ -phase develops from the metastable α -phase after heating and cooling.[Citation20] We will discuss our results in the context of these four phases in more detail below. shows polarised optical micrographs of TESADT films annealed at 100–120°C for 2 min. The crystal domains decrease in size for with a return to amorphous film structure for ((d) and 1(e)). Fan-like structures emerge at ((e)); these appear consistent with the high-temperature β-phase reported by Yu et al.[Citation20] We observe melting of the TESADT and dewetting at much higher anneal temperatures. Our films appear black under POM if raised above 136°C. This indicates a total loss of order resulting in amorphous films, consistent with [Citation20].

Figure 1. POM images for TESADT films annealed at T=(a) 100°C, (b) 105°C, (c) 110°C, (d) 115°C and (e) 120°C for 2 min. The white scale bar in panels (a–d) indicates 100 μm and (e) indicates 1 mm. The post-anneal crystalline domain size decreases for T>100°C with amorphous films obtained for T>115°C.

Figure 1. POM images for TESADT films annealed at T=(a) 100°C, (b) 105°C, (c) 110°C, (d) 115°C and (e) 120°C for 2 min. The white scale bar in panels (a–d) indicates 100 μm and (e) indicates 1 mm. The post-anneal crystalline domain size decreases for T>100°C with amorphous films obtained for T>115°C.

presents an optimisation study with varying time and temperature. TESADT films with single crystal domains of area ∼1 mm2 are obtained for , their thermal history and appearance is consistent with the γ-phase.[Citation24] Crystallisation is strongly diminished at , also consistent with known TESADT γ-phase behaviour, i.e. this phase is heat activated and develops at temperatures above 80°C.[Citation24] For , an anneal time t=2 min is sufficient for wide-spread crystallisation, t=3–5 min produces more optimum results and t>5 min produces minimal further improvement. This timescale for completion of crystallisation is consistent with solvent anneal studies.[Citation14] The optimum anneal condition was 5 min at 90°C. At its best, our thermal anneal process was able to produce visible crystalline domains at scales matching those obtained from parallel processing using solvent annealing instead, as highlighted in (a) and 3(b). This optimum outcome of the thermal anneal tends to vary between TESADT batches though, for reasons that we have, as yet, been unable to determine.

Figure 2. A POM study of domain size versus thermal anneal temperature T (horizontal axis) and time t (vertical axis) for T<100°C. The white scale bars indicate 1 mm. The optimal anneal conditions are T∼ 90°C for t∼ 3 min.

Figure 2. A POM study of domain size versus thermal anneal temperature T (horizontal axis) and time t (vertical axis) for T<100°C. The white scale bars indicate 1 mm. The optimal anneal conditions are T∼ 90°C for t∼ 3 min.

Figure 3. POM images of the best outcomes obtained using optimised (a) thermal- and (b) solvent-annealing processes. The images are composites of 25 smaller overlapping fields to enable the entire 10×10 mm area of the chip to be imaged (n.b., the tile-like contrast changes are an artefact). The white scale bars indicate 2 mm. (c–f) POM sequence showing the effect of alternating thermal (T) and solvent (S) anneals. The sequence begins with a solvent-annealed film (c), the remaining images are obtained after (d) a 2 min thermal anneal at 95°C, (e) a 2 min solvent anneal in dichloroethane vapour and (f) a second 2 min thermal anneal at 95°C. No visible change in the crystalline domain structure is obtained after the initial anneal confirming that both anneals drive towards the same crystal structure.

Figure 3. POM images of the best outcomes obtained using optimised (a) thermal- and (b) solvent-annealing processes. The images are composites of 25 smaller overlapping fields to enable the entire 10×10 mm area of the chip to be imaged (n.b., the tile-like contrast changes are an artefact). The white scale bars indicate 2 mm. (c–f) POM sequence showing the effect of alternating thermal (T) and solvent (S) anneals. The sequence begins with a solvent-annealed film (c), the remaining images are obtained after (d) a 2 min thermal anneal at 95°C, (e) a 2 min solvent anneal in dichloroethane vapour and (f) a second 2 min thermal anneal at 95°C. No visible change in the crystalline domain structure is obtained after the initial anneal confirming that both anneals drive towards the same crystal structure.

Motivated by concerns about photooxidation,[Citation21,Citation22] we also studied how illumination and atmospheric composition affect the outcome of thermal annealing. Interestingly, illumination has a positive effect on crystallisation – films annealed in total darkness show poor crystallisation with typical domain size <50 μm, whereas films annealed under lab light conditions gave the large domains observed in and . The exact origin is unclear, but may indicate an optically induced enhancement in molecular mobility during the anneal process. Note that while UV light has previously been used to selectively dewet TESADT from SiO2 in the presence of dichloroethane vapour,[Citation15] this occurred with high incident intensity: 540 mW/cm2 at 365 nm for 1–2 min. Dickey et al. [Citation15] concluded, based on the intensity used, that dewetting arises from excess thermal energy provided by UV absorption, consistent with the dewetting observed in high-temperature anneals, i.e. . Films thermally annealed under room ambient and pure N2 atmospheres showed little difference in domain size.

These results suggest a complex interplay between solvent interactions and thermal/optical energy during the anneal process. This is also evident in the literature; for example, toluene vapour is an effective annealing agent for TESADT [Citation14] and TESADT orders readily thermally, even at room temperature, if given sufficient time.[Citation18] Yet, the solvent removal bake used in earlier work on solvent-annealed films, [Citation14,Citation19] which involves both solvent vapour and thermal energy, produces only small-grained polycrystalline films, likely in the γ-phase as this bake is performed at 80–90°C. One possibility is that the thermal and solvent anneals drive towards different structural configurations. To test this we took a solvent-annealed film and performed a 2 min thermal anneal at 95°C followed by a 2 min solvent anneal in dichloroethane vapour, and then a second 2 min thermal anneal at 95°C. If the anneals drive towards different configurations then reorganisation of the crystal domains would be expected after each anneal. This does not occur. As (c)–(f) shows, the domain structure is unaffected by subsequent anneals. This behaviour is observed for anneal temperatures up to 120°C where dewetting begins. Shallow-angle X-ray diffraction data for solvent- and thermal-annealed TESADT films both show clear, sharp (00ℓ) diffraction peaks, consistent with earlier work.[Citation13,Citation18,Citation23] These results indicate that all films processed at over 80°C and returned to room temperature end up in the γ-phase. Ultimately though, our findings suggest that a more detailed study of how solvent exposure, heat, substrate surface properties and particularly light influence the ordering kinetics of TESADT is warranted.

3.2. Electronic properties of thermally annealed TESADT thin-film transistors

shows the drain current Id versus drain voltage Vd characteristics obtained at a range of gate voltages Vg for thermal- and solvent-annealed TESADT transistors produced using spin-coated (a and b) and drop-cast (c and d) films. The drop-cast TESADT transistors were studied in an attempt to lessen the electrical impact of heat-induced film cracking, which we discuss in more detail below. The thicker films obtained by drop-casting still suffer from cracking, but the proportion of the conduction channel cross-section lost to fracture and the probability that a given fracture will completely sever some segment of the channel should both be lower. Optimised anneal processes were used in both cases. The films were produced in parallel on nominally identical, pre-prepared transistor substrates: one solvent-annealed with dichloroethane vapour for 2 min, the other thermal annealed at 90°C for 5 min. We discuss the spin-coated device results ((a) and 4(b)) first. The typical Id at a given Vd and Vg is at least two orders of magnitude smaller for the thermally annealed device. The electrical characteristics for thermally annealed devices are more erratic and unstable, as is clear for the Vg=−50 V (top) trace in (b). For solvent-annealed spin-coated films, we obtain a field-effect mobility , comparable to previous reports.[Citation14,Citation15,Citation18,Citation24] In contrast, is typically obtained for thermally annealed films. (c) and 4(d) shows the source–drain characteristics for solvent- and thermal-annealed drop-cast TESADT transistors. Both show improved performance compared with the equivalent spin-coated devices. The gains are more significant for the thermally annealed case: the current at a given Vd and Vg is increased by a factor of 2–3, the characteristics look more typical of a field-effect transistor and show reduced noise. Moving from spin-coated films to drop-cast films approximately doubles the mobility for both anneal types, with typical for thermally annealed samples and for solvent-annealed samples.

Figure 4. The drain current Id versus drain voltage Vd for gate voltages from Vg=−50 V (top) to 0 V (bottom) in steps of 10 V for spin-coated TESADT transistors crystallised using (a) a 2 min solvent anneal in dichloroethane vapour, and (b) a 5 min thermal anneal at 90°C, and for (c and d) drop-cast TESADT transistors crystallised using (c) a 2 min solvent anneal in dichloroethane vapour, and (d) a 5 min thermal anneal at 90°C.

Figure 4. The drain current Id versus drain voltage Vd for gate voltages from Vg=−50 V (top) to 0 V (bottom) in steps of 10 V for spin-coated TESADT transistors crystallised using (a) a 2 min solvent anneal in dichloroethane vapour, and (b) a 5 min thermal anneal at 90°C, and for (c and d) drop-cast TESADT transistors crystallised using (c) a 2 min solvent anneal in dichloroethane vapour, and (d) a 5 min thermal anneal at 90°C.

In , we plot the corresponding transfer characteristics (Id versus Vg at fixed Vd=−30 V) for the four devices in . Our devices are considerably less stable under changing Vg, making it difficult to obtain high-quality transfer characteristics – the resolution of the data in varies from trace to trace due to persistent issues with device stability. To ensure that the obtained transfer characteristics are consistent with the source–drain characteristics, we plot data points obtained at Vd=−30 V for the six different Vg values from in also; the correspondence here is strong. The most obvious aspect of is that the difference between the anneal method is much more significant than the difference between the deposition method. The solvent-annealed films have a much higher on-current, consistent with a higher mobility. They also have more positive threshold voltage, a much lower on–off ratio and a significantly reduced subthreshold slope – the values we obtain for these various device performance metrics are compiled in .

Figure 5. The drain current Id versus gate voltage Vg for drain voltage Vd=−30 V for each of the four different TESADT transistors in . The lines are measured transfer characteristics. The data points are extracted directly from to demonstrate correspondence between the transfer and source–drain characteristics for the four devices.

Figure 5. The drain current Id versus gate voltage Vg for drain voltage Vd=−30 V for each of the four different TESADT transistors in Figure 4. The lines are measured transfer characteristics. The data points are extracted directly from Figure 4 to demonstrate correspondence between the transfer and source–drain characteristics for the four devices.

Table 1.  Key electrical performance parameters for the four types of TESADT thin-film transistors studied.

While it is tempting to attribute the poorer performance in our thermally annealed films to reduced crystal domain size and the reduced electrical performance of the TESADT γ-phase compared with other phases, e.g. the α-phase,[Citation20] we believe there is an additional and potentially more significant effect responsible – thermally induced cracking of the film during the thermal anneal process. We studied this using a polarised optical microscope with a hotplate stage. This enabled us to continuously monitor the thermal anneal process. Visible cracks develop at and persist after cooling to room temperature. To demonstrate the problem most clearly, (a) and 6(b) shows images of a solvent-annealed TESADT film immediately before (a) and immediately after (b) thermal annealing at 90°C for 5 min. The post-annealed film in (b) shows numerous cracks, highlighted by the arrows, which were not present in the pre-annealed film. Note well that this problem is not isolated to previously solvent-annealed films; amorphous, as-deposited films show the same behaviour, but the cracks are more difficult to see due to the much higher density of grain boundaries in α-phase films. There is also no visible change in domain structure between (a) and 6(b), suggesting that if a change in crystallite phase does occur with solvent annealing, it is invisible to POM. Together these two observations strongly point to thermal expansion being the leading cause of film cracking. However, further studies, e.g. by variable temperature wide-angle X-ray scattering, would be needed to comprehensively rule out the possibility that polymorph transitions might accelerate cracking in crystalline films. As a final note, we have been unable to remove these cracks by subsequent solvent or thermal annealing; they appear to be a permanent feature of films annealed to .

Figure 6. POM images (a) before and (b) after thermal annealing of a solvent-annealed TESADT film. The black and white arrows in (b) indicate cracks that developed during thermal annealing. (c) The field-effect mobility μ versus maximum anneal temperature for a TESADT transistor that underwent subsequent 2 min thermal anneals at T=30, 40, 50, 60, 70, 80 and 90°C, with electrical measurements performed at 25°C between each anneal. The initial point at T=25°C indicates a sample measured prior to any thermal annealing.

Figure 6. POM images (a) before and (b) after thermal annealing of a solvent-annealed TESADT film. The black and white arrows in (b) indicate cracks that developed during thermal annealing. (c) The field-effect mobility μ versus maximum anneal temperature for a TESADT transistor that underwent subsequent 2 min thermal anneals at T=30, 40, 50, 60, 70, 80 and 90°C, with electrical measurements performed at 25°C between each anneal. The initial point at T=25°C indicates a sample measured prior to any thermal annealing.

We finish by briefly discussing the effect of reduced thermal anneal temperature on the electrical properties of drop-cast TESADT transistors to provide some further confirmation that the cracks that develop for thermal anneals at are responsible for the reduced mobility. (c) shows the measured mobility versus maximum anneal temperature for a single device subject to anneals at increasing temperatures from 30°C to 90°C. To be specific, we obtain electrical measurements at 25°C, anneal for 2 min at 30°C, obtain electrical measurements at 25°C, anneal for a further 2 min at 40°C, measure again at 25°C, etc., continuing with anneal temperature increments of 10°C until we reach 90°C. We do this in a single device to avoid device–device variations from influencing the results. We find a small increase in mobility with thermal annealing until the anneal temperature exceeds 40°C. The mobility declines thereafter, dropping precipitously for , where thermally induced cracking becomes more prevalent providing confirmation that film cracking adversely affects electrical performance.

The data in (c) suggest that one possible idea to salvage the use of thermal annealing, namely performing much longer anneals (∼ hours) at temperatures well below 75°C, is likely of limited potential. The temperature would need to be below 40°C according to (c), and at that point, one might as well either wait the three to seven days required for spontaneous order to develop at room temperature,[Citation18] resort to solvent annealing [Citation14] or take what currently appears to be the most favourable option, which is low-temperature casting of the TESADT film to obtain the metastable α-phase. The latter gives more consistently favourable electrical characteristics compared with the γ-phase obtained in transistors with TESADT films that have undergone high-temperature processing.[Citation19,Citation20]

4. Conclusions

We studied thermal annealing for post-deposition crystallisation of TESADT films for organic transistor applications. Under ideal circumstances thermal annealing produces mm-sized domains comparable in size to established solvent annealing methods.[Citation14] The ideal anneal condition was 5 min at 90°C. The thermal anneal crystalline packing matches that for the solvent anneal, which is likely the TESADT γ-phase based on thermal history and appearance under POM.[Citation20] Repeated annealing by either approach produces no further change in domain structure. Unfortunately, the thermal anneal gives much less improvement in the electrical performance compared with solvent annealing. For spin-coated films we obtained mobilities of order and for thermal- and solvent-annealed devices, respectively. Both mobility values approximately double for drop-cast films. We attribute the comparatively poor electrical performance of thermally annealed TESADT to film cracking during the thermal anneal process. This occurs over and above any polymorph-related performance losses.[Citation20] POM reveals that cracking occurs above 75°C; these cracks persist upon cooling and even if the film is solvent-annealed thereafter. Electrical measurements suggest this problem begins at temperatures as low as 40°C; the cracks developed for are likely too small to clearly observe optically. The cracking is likely due to the difference in the thermal expansion coefficient between the TESADT and the underlying SiO2/Si substrate. It might be resolved using either flexible substrates (e.g. polyimide films) or substrates with a similar thermal expansion coefficient to TESADT.

As a final point, we also note that illumination has a significant positive effect on crystallisation with thermal annealing. Films annealed in total darkness show poor crystallisation with typical domain size <50 μm, whereas films annealed under lab light conditions give domains up to 1 mm wide. This may indicate an optically induced enhancement in molecular mobility during annealing and suggests that further studies of how solvent, heat, substrate surface properties and in particular, light exposure influence the ordering kinetics of TESADT are warranted.

Acknowledgements

A.P.M. acknowledges the Australian Research Council (FT0990285) and J.E.A. acknowledges the National Science Foundation (DMR1035257) for support. This work was performed in part using the NSW node of the Australian National Fabrication Facility (ANFF). We thank A.R. Hamilton and P. Meredith for helpful discussions. K. Muhieddine and R.W. Lyttleton contributed equally to this work.

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