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Electrical & Electronic Engineering

Neural network detector with sparse codes for spin transfer torque magnetic random access memory

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Article: 2231724 | Received 31 Dec 2022, Accepted 27 Jun 2023, Published online: 03 Jul 2023

Abstract

This paper presents leveraging the neural network detector to improve the performance of a spin transfer torque magnetic random-access memory (STT-MRAM), where the sparse coding scheme is also applied to protect the user data for the asymmetric write failure. The STT-MRAM has recently emerged as a good candidate, attracting the attention of both academia and industry because of its unique features such as density, non-volatility, power consumption, and integration with CMOS technology. The reliability of STT-MRAM is degraded significantly by reading and writing failures. The asymmetric write failure is the primary contributor to write errors in STT-MRAM. This issue arises from a higher error rate when switching from 0 (low resistance) to 1 (high resistance), as compared to switching from 1 to 0. The sparse coding scheme can be employed, which ensures that the codeword weight is always less than half of the codeword length. By reducing the frequency of encountering “1,” this method minimizes the occurrence of 0 ➔ 1 switching, which in turn reduces the rate of writing failure for the STT-MRAM system. The neural network detector offers better performance than the threshold detector and significantly tackles the system’s unknown offset. Simulation results show the proposed scheme can provide improvements for the reliability of STT-MRAM under the effect of both write and read errors. For instance, the proposed model can handle a read error rate of approximately 9%, whereas the traditional thresholding solution only allows about 6%. Moreover, the proposal eliminates the error propagation in retrieving the original information.

1. Introduction

Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising technologies for next-generation non-volatile memory (NVM) systems. Flash and dynamic RAM (DRAM) are now leading in electronic memory. However, the problem of the write/erase (W/E) cycles is hugely challenging for Flash systems. The reliability of the device is significantly degraded due to the W/E being over the limit. Moreover, DRAM cannot provide a non-volatile feature and has high power consumption due to the significant effect of inevitable leakage current. The STT-MRAM has arrived as a leading candidate for stand-alone and embedded NVM applications among various emerging NVM technologies (H. Cai et al., Citation2021). Significantly, due to attractive advances such as durable and non-volatile devices or nanosecond read and write processes, the STT-MRAM is very useful in many applications, such as consumer electronics devices, cache in mobile devices, and IoT/AI devices.

On the way to becoming the dominant NVM device, STT-MRAM also addresses its challenges. Besides manufacturing and scaling technology issues, STT-MRAM faces the two most challenging technical problems, the asymmetric write error (AWE) and unknown offsets of the system.

The AWE is a unique feature of the STT-MRAM structure. The error probability of a 1 to 0 transition tends to be much lower than that of a 0 (low resistance) to 1 (high resistance) transition. A write error can occur when there is insufficient switching current to complete the required switching process before the MTJ switching process finishes. This can result in multiple or entire memory cells failing to transition from 1 to 0 or 0 to 1. This phenomenon occurs due to insufficient current being applied to generate the write pulse required for the switching process, which is caused by thermal fluctuations and process variations. Evaluations of the write error rate have been shown in (Azad et al., Citation2019; Shiota et al., Citation2016; Shreya & Kaushik, Citation2020), and as reported in (Azad et al., Citation2019), the write error probability is asymmetric.

The reliability of transmission and storage channels is significantly embarrassed by unknown offset or drift (K. A. Immink & Cai, Citation2020). The deviation, or offset, from the nominal values of memory readback signals, such as resistance or voltages, are unknown to both the sender and receiver. The unknown offset of the storage channel is a critical issue for many NVM systems. The main reason for the unknown offset for STT-MRAM is the thermal fluctuations (Wu et al., Citation2016). Based on simulation results at different temperatures, it has been shown that the read error becomes more significant if the temperature increases. In other words, the overlap area of voltage distributions is more significant in proportion to the temperature. Under adverse circumstances, such as process variations or unforeseeable biasing conditions, the AWE and unknown offset become much more severe.

Spintronics-based memories have potential errors due to the sensitivity of the spin states to external perturbations. Hamming codes or BCH codes (Jiang et al., Citation2022; Zhang et al., Citation2023) are commonly used to correct such errors. Moreover, other error-correcting codes have been researched to enhance the performance of non-volatile memories (K. Cai & Schouhamer Immink, Citation2017; Everspin Technologies MR4A16B Features, Citation2021). It has been reported that conventional error-correction codes (ECCs), such as Hamming and BCH codes, offer the same error-correcting capability for both bit-flipping directions (Wen et al., Citation2013). Modulation codes are already widely used in next-generation data storage systems (C. D. Nguyen, Citation2020; C. D. Nguyen et al., Citation2021; Shao et al., Citation2018). They are regarded as one of the best approaches to overcoming the AWE and unknown offset challenges.

Advanced channel detection schemes have been suggested to improve the bit error rate (BER) performance for the next-generation ultra-high-capacity information storage systems (Busyatras et al., Citation2015; Chang et al., Citation2002; Myint & Supnithi, Citation2012; C. D. Nguyen & Lee, Citation2015). To deal with the effect of unknown offsets, the usual approach is to use extrinsic information to estimate this offset. These traditional approaches have been somewhat effective, but the system architecture has become more complicated by including the offset estimation part. Recently, artificial neural networks have proven highly effective in many areas such as computer vision, image processing, and many other areas (Goodfellow et al., Citation2016; Han et al., Citation2019; C. D. Nguyen et al., Citation2021; Park et al., Citation2021). Neural networks are also well-known as valuable tools in modeling nonlinear functions. The multilayer perceptrons (MLP) model, one of the most prominent deep learning models, has also been proposed for equalizing nonlinear or estimating track misregistration storage channels (Han et al., Citation2019). The obtained results have shown significant improvements in reducing the nonlinear effects caused by media noise and unknown offset.

This paper proposes applying sparse codes for the user signal before writing to the STT-MRAM cell and detecting the received signal by an MLP-based detector. Moreover, the output of the MLP-based detector is decoded based on a modified Pearson distance. Thus, the proposed model is to conduct two techniques simultaneously to improve the performance of STT-MRAM.

The remainder of this paper is organized as follows. Section II presents the STT-MRAM operation and its adopted channel model. The proposed structure, including the sparse code and MLP-based detector, is analyzed and presented in Section III. Simulation results and discussion are shown in Section IV. Section V delivers the concluding remarks.

2. STT-MRAM operation and cascaded channel model

2.1. STT-MRAM operation

A typical STT-MRAM cell structure and its corresponding switchings are illustrated in Figure . In general, the STT-MRAM cell consists of a magnetic tunnel junction (MTJ) (Girard et al., Citation2021) connected in series with the nMOS access transistor, said one-transistor one-MTJ (1T1J). The MTJ is a sandwich model. In other words, it consists of one ultrathin oxide layer placed between two main ferromagnetic layers. One of the ferromagnetic layers is magnetized in a fixed orientation, said a reference layer. The other layer, whose magnetization can be freely changed, is denoted as a free layer. The MTJ cell represents two resistance values. When the magnetic orientation of the reference layer is parallel (antiparallel) to that of the free layer, the MTJ is in a low (high) resistance state. The low (R0) and high (R1) resistance states present a bit logic of 0 and a bit logic of 1, respectively. It is important to note that a passing current through the MTJ for writing and reading is needed, as seen in Figure .

Figure 1. STT-MRAM cell structure. a) 1 to 0 transition. b) 0 to 1 transition.

Figure 1. STT-MRAM cell structure. a) 1 to 0 transition. b) 0 to 1 transition.

The reliability of the STT-MRAM operations is deteriorated significantly by both read and write errors. As mentioned previously, it is well-known that the AWE is the primary contributor to write errors in STT-MRAM. The read errors are often caused by incorrect sensing of the memory cell resistance and the effect of an undesirable large current.

2.2. Cascaded STT-MRAM channel model

In this work, we used the STT-MRAM cascaded channel model suggested by Cai and Immink (Wu et al., Citation2016). The cascaded model is a combination of models of the write error and read error. First, let P1, P0, and Pr denote the write failure probability of 0 to 1 transitions, the write failure probability of 1 to 0 transitions, and the read disturb failure probability, respectively. Thereby,

  • The write error is modeled by a binary asymmetric channel (BAC), where the failure probabilities of 0 to 1 transitions and 1 to 0 transitions of the BAC are given by P0/2 and P1/2, respectively.

  • A Z channel having the read disturb failure probability Pr of 1 to 0 transitions is used to present the read disturb error.

  • A Gaussian mixture channel (GMC) is adopted to model the read decision error, thereby R0 Nμ0,σ0 and R1 Nμ1,σ1, where the μ0,σ0 and μ1,σ1 pairs are the mean and standard deviation pairs of resistances, respectively.

Figure illustrates a block diagram of the cascaded channel model under a write-0 direction. A combination of the BAC and Z models can be implemented straightforwardly, and the crossover probabilities can be presented as follows,

p0=P021Pr;p1=P12+1P12Pr
(1) q0=1P02+P02Pr;q1=1P121Pr(1)

Figure 2. Cascaded STT-MRAM model, for reading with write-0 direction. WEM: write error model; REM: read disturb error model; GMC: Gaussian mixture channel.

Figure 2. Cascaded STT-MRAM model, for reading with write-0 direction. WEM: write error model; REM: read disturb error model; GMC: Gaussian mixture channel.

Furthermore, an offset of resistance caused by the temperature change occurring to the high resistance state is considered in this paper. We also adopt a Gaussian distribution parametrized by μofs and σofs to model the offset. Figure shows a block diagram of applying the sparse code and MLP-based detector to the STT-MRAM system.

Figure 3. Block diagram of system model.

Figure 3. Block diagram of system model.

3. Proposed scheme of sparse coding and MLP-based detector for STT-MRAM

3.1. Potential sparse codes

The sparse codes are defined as those where the proportion of logic 1 is less than 1/2. As the failure probability of 0 to 1 transition tends to be higher than that of 1 to 0 transition, minimizing the number of logic 1 of the stored data sequence through the encoding can improve the system performance. The asymmetric write failure rate of STT-MRAM can be lowered using the potential coding scheme. This study applies the 7/9 sparse code proposed in (C. D. Nguyen, Citation2021) to overcome the AWE. Thereby, encoding 7-bits user-data sequences into 9-bits codewords, such that the codewords have their weight of 2 and 4 only, is accomplished by the proposed encoder.

According to (C. D. Nguyen, Citation2021), the maximum likelihood (ML) decoding is applied for the 7/9 sparse code to recover the user information. The Euclidean distance of a received codeword cˆ to a codeword c of the codebook Sw can be calculated as follows,

(2) dcˆ,c=cˆc2(2)

However, the Euclidean-distance-based approach can be distorted, resulting in a loss in noise margin or even a complete loss of the codewordunder the effect of offset (K. A. S. Immink & Weber, Citation2014; Schouhamer Immink et al., Citation2018). Therefore, we propose a minimum Pearson-distance-based decoder for decoding the 7/9-rate sparse code to improve the system performance under an unknown offset.

First, the Pearson distance δpcˆ,c between the received vector cˆ and a candidate codeword cSw, both in the length of n, can be defined as,

(3) δPcˆ,c=1χcˆ,c(3)

where the χcˆ,c is the Pearson correlation coefficient,

(4) χcˆ,c=i=1ncˆicˆcicσcˆσc(4)

where the mean c and σc2 variance values of c are defined as follows,

(5) c=1ni=1nci,σc2=i=1ncic2(5)

The mean cˆ and σcˆ2 variance values of cˆ are defined similarly. The Pearson distance lies in the interval [0,2]. By a slight manipulation of (3), a modified Pearson distance can be obtained as follows,

(6) δmPcˆ,c=i=1ncˆici+c2(6)

A minimum Pearson distance-based decoder operates the same way as the traditional minimum Euclidean detector. The decoder calculates the Pearson distance between cˆ and c, for all cSw. The codeword cr yielding the minimum δmPcˆ,c is regarded as the transmitted codeword, or in other words,

(7) cr=argmincSwδmPcˆ,c(7)

Finally, a de-mapping operation is applied to retrieve the original user data uˆ.

3.2. MLP-based detector architecture

In this part, we present the proposed MLP-based detection scheme. The MLP scheme is a feedforward deep neural network with a complete layer connection. The method has been proposed for equalizing nonlinear or estimating track misregistration storage channels (Han et al., Citation2019). As can be seen in Figure , the user-data signal u is first encoded by the 7/9 sparse encoder, then the output codewords of the encoder are recorded on the STT-MRAM channel. During retrieving, the falsified output of the STT-MRAM channel r, which is the resistance values r=ri,1,ri,2,ri,3,,ri,N, where N is the number of neurons at the input layer, is fed into the MLP-based detector. In this study, we set up N=9, precisely the length of the transmitted codeword.

The proposed MLP architecture consists of four layers, an input layer of size N, two hidden layers of size N2, and an output layer of size N. This architecture is shown in Figure . After adding up the inputs with the weights and biases of the hidden layer neurons, a nonlinear activation function is applied to establish the non-linearity to the neural network. We use a rectified linear unit (ReLU) and sigmoid activation functions for the hidden and output layers, respectively.

Figure 4. Proposed architecture of MLP model.

Figure 4. Proposed architecture of MLP model.

The output of the MLP model can be expressed as a function of the MLP input and the system parameters Θ as follows,

(8) cˆ=fr,Θ(8)

The target of the MLP model is to find the best network parameters Θ such that the cost function, which evaluates the “good” of the model, is to be minimized. It means,

(9) Θ=argminΘLc,cˆ(9)

where L is the cost function. The cost function L can be thought of as the objective function in the training process. The model’s prediction results are more accurate the more this function is minimized.

The system configuration parameters of the proposed MLP architecture are determined by experiment. After many trial-and-error processes, we find that 1×105N training samples are sufficient to achieve the best performance. To illustrate the neural network training process, we have simulated the BER of the MLP-based detector for each epoch during training, where, σ0/μ0=8%, μofs=0.2kΩ, and σofs/μ1=4%. In Figure , it can be observed that when the epoch increases, the training BER of the detector decreases. After reaching a certain number of epochs, the BER converges. We used 30 epochs in this paper. Table shows the system configuration parameters of the proposed MLP architecture.

Figure 5. BER of the MLP-based detector for each epoch during training.

Figure 5. BER of the MLP-based detector for each epoch during training.

Table 1. Parameters of the proposed MLP architecture

4. Simulation and discussion

We used experimental parameters (K. Cai & Schouhamer Immink, Citation2017; Mei et al., Citation2019) for simulating the STT-MRAM channel. Thereby, we adopted the values of μ0=1kΩ, μ1=2kΩ, and σ0/μ0=σ1/μ1. Changing the ratio σ0/μ0 (and hence σ1/μ1) reflects the severity of the read decision errors. Assume that a fixed write failure probability of P1=2×104, and the error probabilities of P0 and Pr are two orders of magnitude lower than P1 (Wu et al., Citation2016). The neural network library Keras (Chollet, Citation2015) combined with the deep learning library TensorFlow (Google Brain, Citation2015) is deployed in this paper. The training is conducted offline. To train the MLP-based detector under the STT-MRAM channel model, we generate sufficient data samples of the memory readback resistance r and its corresponding label c as the training data set. The data is generated through computer simulation only. We do not apply the preprocessing and regularization techniques in this proposed model. The proposed MLP model, after training and evaluation, is used to detect its input samples r and generate the prediction of the channel input cˆ without any prior knowledge of the STT-MRAM channel, as represented in (8) and (9).

Figure shows the BER performance of the proposed scheme with the Euclidean-distance-based decoding. We investigate the proposed model in two cases: a) using a traditional threshold channel detector, the threshold of μ0+μ1/2; b) using the MLP-based detector. It is straightforward to observe that the error propagation occurs using a traditional threshold channel detector. The performance at the detector output is improved compared to the case of the system without coding due to the effectiveness of the 7/9-rate sparse code. However, the BER performance of the decoder output is worse than that of the detector output. The bit errors of the detector output cause severe burst errors during the decoding procedure. In the case of using the MLP-based detector, the performance of both the detector and decoder has been improved significantly. The effect of error propagation is eliminated.

Figure 6. BER comparison without offset.

Figure 6. BER comparison without offset.

Figure illustrates the BER performance of the proposed scheme with the Euclidean-distance-based decoding under the offset effect of μofs=0.2kΩ and σofs/μ1=4%. A similar result is obtained in the absence of the offset effect. The propagation error occurs when the MLP-based detector is not used. First, the BER performance at the detector output, using the 7/9 sparse code and w/o MLP-based detector, is better than the case without coding. This indicates that, under the same threshold detector, using the 7/9 sparse code significantly avoids the AWE effect compared to the system without coding. As a result, the BER improvement at the detector output is apparent. The problem occurs during the decoding. Since the traditional approach to decoding the 7/9 sparse code is based on Euclidean, which is not resistant to the unknown offsets, an error propagation causes the decoder output becomes significantly worse. Error bits at the detector output trigger more severe error bursts in the decoding. The performance is greatly improved at both the detector output and the decoder output in the case of using the MLP-based detector.

Figure 7. BER comparison, offset of μofs=0.2 and σofs/μ1=4%.

Figure 7. BER comparison, offset of μofs=−0.2kΩ and σofs/μ1=4%.

Finally, we estimate the BER performance of the proposed scheme with the modified Pearson-distance-based decoding. The simulation results, under the offset effect of μofs=0.2kΩ and σofs/μ1=4%, have been shown in Figure . There is no error propagation even though the MLP-based detector is not deployed. Table shows the corresponding BERs for various severity ratios of read decision errors under the offset condition. This shows the beneficial effect of using Pearson distance in decoding,taking into account the offset effect. The performance continues to improve significantly when the MLP-based detector is implemented. We have compared our proposed model to (Mei et al., Citation2019), and our findings show that it is more efficient in several aspects. The proposed system showcases a significant reduction in network parameters, around five times fewer than the number of parameters in (Mei et al., Citation2019). With the tuning of decoding techniques, we were able to minimize the negative impact of propagation errors which helped improve the performance of BER, without having to rely on an MLP-based detector. Additionally, our proposal excels in tolerating the severity of read decision errors, especially as the levels of errors increase. This improvement is highlighted in Table .

Figure 8. BER comparison, offset of μofs=0.2 and σofs/μ1=4%.

Figure 8. BER comparison, offset of μofs=−0.2kΩ and σofs/μ1=4%.

Table 2. BER comparison for offset of μofs=0.2kΩ and σofs/μ1=4% between pearson-based decoding and Euclidean-based decoding

Table 3. BER comparison between the proposed model and ref [27] at offset of μofs=0.2kΩ and σofs/μ1=4%

It is also important to note that, as seen in Figures , if the value of σ0/μ0 (and hence σ1/μ1) increases (the channel state is worse,) the system performance degrades, and the performance of the detector and decoder tends to converge. Therefore, a better neural network model with reasonable complexity needs attention to improve the STT-MRAM further, especially when the read errors are much more severe. In addition, building error-correcting modulation codes or combining the proposed 7/9 sparse code with the existing error-correcting codes as in (K. Cai & Schouhamer Immink, Citation2017; Everspin Technologies MR4A16B Features, Citation2021; Wen et al., Citation2013) raises the system’s complexity but helps significantly improve the BER of the system and enhances the reliability in data recovery.

5. Conclusion

In this work, we develop a simple but efficient structured sparse modulation code for reducing the effect of AWE and offset for STT-MRAM. The sparse code reduces the occurrence of “1,” resulting in a marked decrease in the rate of writing failures. The simulation results have shown that the sparse code works very well when applied to the STT-MRAM channel. Pearson-based decoding allows achieving resilience against unknown offset while minimizing the impact of error propagation. We also propose the application of MLP-based detection to further improve the performance of the STT-MRAM storage channel under the effect of unknown offset. The MLP-based signal detector exhibits superior performance over the conventional scheme. For instance, considering the severity of read decision errors at σ0/μ0=7%, the proposed system’s decoder output performance can reach a BER of approximately 104, compared to the traditional system without MLP, which only achieves an error rate of BER of about 102. This shows great potential for applying artificial neural networks to overcome the AWE and unknown offset effects for STT-MRAM systems.

Acknowledgments

This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 102.04-2019.307.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

The work was supported by the Vietnam National Foundation for Science and Technology Development (NAFOSTED) [102.04-2019.307].

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